74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
Rev. 3 — 28 March 2014
Product data sheet
1. General description
The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four
mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE).
When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data
input for a 1-to-4 demultiplexer application. Inputs include clamp diodes that enable the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC139: CMOS level
For 74HCT139: TTL level
Demultiplexing capability
2 independent 2-to-4 decoders
Multifunction capability
Suitable for memory decoding, data routing or code conversion
Complies with JEDEC standard no. 7A
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC139N
74HCT139N
74HC139D
74 HCT139D
74HC139DB
74HCT139DB
74HC139PW
74HCT139PW
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
NXP Semiconductors
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Functional diagram
a.
b.
Fig 3.
IEC Logic symbol
74HC_HCT139
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 28 March 2014
2 of 18
NXP Semiconductors
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
Fig 4.
Logic diagram (one decoder/demultiplexer)
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration DIP16, SO16, SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
1E, 2E
1A0, 1A1
1Y0, 1Y1, 1Y2, 1Y3
GND
2Y0, 2Y1, 2Y2, 2Y3
2A0, 2A1
V
CC
Pin description
Pin
1, 15
2, 3
4, 5, 6, 7
8
12, 11, 10, 9
14, 13
16
Description
enable input (active LOW)
address input
output (active LOW)
ground (0 V)
output (active LOW)
address input
positive supply voltage
74HC_HCT139
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 28 March 2014
3 of 18
NXP Semiconductors
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
6. Functional description
Table 3.
Control
nE
H
L
L
L
L
[1]
Function table
[1]
Input
nA1
X
L
L
H
H
nA0
X
L
H
L
H
Output
nY3
H
H
H
H
L
nY2
H
H
H
L
H
nY1
H
H
L
H
H
nY0
H
L
H
H
H
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 package
SSOP16 package
TSSOP16 package
[1]
[2]
[3]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
[1]
[2]
[3]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
50
65
-
-
-
-
Max
+7
20
20
25
50
-
+150
750
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
mW
74HC_HCT139
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 28 March 2014
4 of 18
NXP Semiconductors
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC139
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT139
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25
C
Min
74HC139
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
-
-
-
-
-
-
0
0
0
0.15
0.16
-
0.1
0.1
0.1
0.26
0.26
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
V
V
V
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Typ
Max
T
amb
40 C
to +85
C 40 C
to +125
C
Min
Max
Min
Max
Unit
74HC_HCT139
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 28 March 2014
5 of 18
嵌入式系统
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