BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
4 MEGABIT (512K x 8)
5 VOLT SECTOR ERASE CMOS FLASH MEMORY
GENERAL DESCRIPTION
The BM29F040 is a 4 Megabit, 5.0 Volts only Flash memory device organized as 512K
×
8 bits each.
The BM29F040 is offered in an Industry standard 32-pin package which is backward compatible to 1
Megabit and also pin compatible to EEPROMs. The device is offered in PDIP, PLCC and TSOP
packages. The device is designed to be programmed and erased in system with the standard system
5 Volt Vcc supply. An external 12.0 Volts Vpp is not required for program and erase operation. The
device can also be reprogrammed in standard EPROM programmers.
The BM29F040 offers access times between 70 to 150 nS. The device has separate chip enable
( CE ), write enable (
WE
) and output enable ( OE ) controls to eliminate bus contention.
BMI flash memory technology reliably stores memory information even after 100,000 erase and
program cycles. The BMI proprietary cell technology enhances the programming speeds and
eliminates over erase problems seen in the classical ETOX
™
type of Flash cell technologies. The
combination of cell technology and internal circuit design techniques give reduced internal electrical
fields and this provides improved reliability and endurance. The BM29F040 is entirely pin and
command set compatible to the JEDEC standard 4 Megabit EEPROM. The commands are written to
the Command State machine using standard microprocessor write timings. The internal Programming
and Erase Algorithms are automatically implemented based on the input commands.
The BM29F040 is programmed by executing the program command sequence. This will start the
internal automatic program Algorithm that times the program pulse width and also verifies the proper
cell margin. Erase is accomplished by executing the erase command sequence. The internal Power
Switching State Machine automatically executes the algorithms and generates the necessary voltages
and timings for the erase operation. The program and erase verify is also done internally and proper
margin testing is automatically performed. This scheme unburdens the microprocessor or
microcontroller from generating the program and erase algorithms by controlling all the necessary
timings and voltages. The entire memory is typically erased in 1.5 seconds. No preprogramming is
necessary in this technology.
The BM29F040 also features a sector erase architecture. It is divided into 8 sectors of 64K bytes
each. Each sector can be erased individually without affecting the data in other sectors or they can be
erased in a random combination of groups. This multiple sector erase capability or full chip erase
makes it very flexible to alter the data in BM29F040. To protect the data from accidental program or
erase the device also has a sector protect or multiple sector protect function.
The device features a single 5 Volt power supply for read, program and erase operation. Internally
generated and well regulated voltages are provided for the program and erase operation. A low Vcc
detector inhibits write operations during power transitions. The end of program or erase is detected by
Data polling of DQ7 or by the Toggle Bit feature on DQ6. Once the program or erase cycle has been
successfully completed, the device internally resets to Read mode.
A Winbond Company
-1-
Publication Release Date: May 1999
Revision A1
BRIGHT
Microelectronics
Inc.
FEATURES
•
Preliminary BM29F040
5.0 V +/- 10% Program and Erase
−
Minimizes system power consumption
−
Simplifies the system design
•
Sector Erase architecture
−
8 Equal sectors of 64K bytes each
−
Any combination of multiple Sector Erase
−
Full Chip Erase
•
Compatible with JEDEC standard commands
−
Uses same software commands as
EEPROMs
•
Sector Protection
−
Any number of sectors can be protected from
Program and Erase operation
•
Compatible with JEDEC-standard byte wide
pinout
−
32 pin PLCC/TSOP
−
32 pin DIP
•
•
•
Low Power Consumption
Typically 100,000 Program/Erase cycles
Erase Suspend and Resume
−
Suspend the Sector Erase Operation to
allow a READ in another sector
•
Automated sector/chip Erase Algorithms
−
No programming before Erase needed
−
Internal program and Erase Margin Check
•
•
Low Vcc Write inhibit
<
3.2 volts
Single Cycle reset command
•
Data Polling and Toggle Bit
−
useful for detection of Program and Erase
cycle completion
Product Selection Guide
FAMILY PART NO:
Maximum Access Time (nS)
CE (E) Access time (nS)
OE (G) Access time (nS)
-75*
70
70
30
Table 1
-90
90
90
35
-120
120
120
50
-150
150
150
60
*This speed is available with Vcc = 5V +/- 5% variation
-2-
BRIGHT
Microelectronics
Inc.
PIN CONFIGURATIONS
DIP Top View
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
Preliminary BM29F040
Vcc
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Top View
A12 A16 Vcc A17
A15 A18 WE
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
14 15 16 17 18 19 20
I/O's 1 2 GND3 4 5 6
TSOP Top View
TYPE 1
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/07
I/06
I/05
I/04
I/03
GND
I/02
I/01
I/00
A0
A1
A2
A3
A Winbond Company
-3-
Publication Release Date: May 1999
Revision A1
BRIGHT
Microelectronics
Inc.
Flexible Sector-erase Architecture:
64K bytes per sector
Individual sector, multiple sector or bulk erase capability.
Individual or multiple-sector protection is user definable.
Table 2. Sector Definition
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
70000H-7FFFFH
60000H-6FFFFH
50000H-5FFFFH
40000H-4FFFFH
30000H-3FFFFH
20000H-2FFFFH
10000H-1FFFFH
00000H-0FFFFH
Preliminary BM29F040
PIN DESCRIPTION
SYMBOL
A
0
- A
18
A
9
DQ
0
-DQ
7
TYPE
I
I
I/O
NAME AND FUNCTION
ADDRESS INPUTS:
for memory addresses. Addresses are internally
latched during a write cycle.
ADDRESS INPUT:
When A
9
is at 12 Volts the ID mode is accessed. During
this mode A
0
decodes between the manufacturer and device ID′s.
DATA INPUTS / OUTPUTS:
Inputs array data on the fourth
CE
and
WE
cycle during a program command. Inputs commands
WE
to the Command
register when
CE
and
WE
are active. Data is internally latched during the
program cycles. Outputs are from Array and Intelligent Identifier
information. The output pins float to tri-state when the chip is deselected or
the outputs are disabled.
CHIP ENABLE:
Activates the device's control logic, input buffers, decoders
and sense amplifiers.
CE
is active low control;
CE
high deselects the
memory device and reduces power consumption to standby levels.
OUTPUT ENABLE:
OE
is active low control signal. This pin gates the
device
’s
outputs through the data buffers during a read cycle. When
CE
is
low and
OE
is high the outputs are tri-state.
WRITE ENABLE:
Controls writes to the Command state Machine and
memory array.
WE
is active low signal. Addresses and Data are latched
during the rising edge of the
WE
pulse.
DEVICE POWER SUPPLY:
Main power source to the device. It′s value is
5V
±
10% or 5V
±
5%.
GROUND:
The device ground for the internal circuitry.
Table 3
CE
I
I
OE
I
WE
Vcc
GND
-4-
BRIGHT
Microelectronics
Inc.
BLOCK DIAGRAM
Preliminary BM29F040
DQ
0
- DQ
Vcc
GND
Erase Voltage
Generator
7
Input / output
Buffers
WE
State
Control
Command
Register
Program Voltage
Generator
CE
OE
Vcc Detect
Timer
A
d
d
r
e
s
s
L
a
t
c
h
Chip Enable
Output Enable
Logic
Data
latch
Y-Decode
Y-MUX / SENSING
X-decode
ARRAY
A
0
- A
18
Figure 1
BUS OPERATION
Operation
Auto select Manufacturers ID (1)
Auto select Device ID (1)
Read
Standby
Output Disable
Write
Enable Sector Protect
Verify Sector Protect (3)
CE
OE
WE
A0
L
H
A
0
X
X
A
0
X
L
A1
L
L
A
1
X
X
A
1
X
H
A6
L
L
A
6
X
X
A
6
X
L
A9
V
ID
V
ID
A
9
X
X
A
9
V
ID
V
ID
I/O
Code
Code
Dout
High Z
High Z
Din (2)
X
Code
L
L
L
H
L
L
L
L
L
L
L
X
H
H
V
ID
L
H
H
H
X
H
L
L
H
Table 4
Notes:
1. LEGENDS: L = V
IL
, H = V
IH
, X = don't care, V
ID
= +12V.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to table 6 for
Command definitions.
3. Refer to Table 4 for valid Din during a write operation.
4. Refer to the section on sector protection.
A Winbond Company
-5-
Publication Release Date: May 1999
Revision A1
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