74ALVCH16244
Low−Voltage 16−Bit Buffer
with Bus Hold 1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16244 is an advanced performance, non−inverting
16−bit buffer. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16244 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16−bit operation. The 3−state outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bushold
circuitry, eliminating the need for external pull−up resistors to hold
unused or floating inputs at a valid logic state.
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MARKING DIAGRAM
48
48
1
74ALVCH16244DT
AWLYYWW
TSSOP−48
DT SUFFIX
CASE 1201
A
•
Designed for Low Voltage Operation: V
CC
= 1.65
−
3.6 V
•
3.6 V Tolerant Inputs and Outputs
•
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
•
•
•
•
•
•
•
•
1
= Assembly
3.7 ns max for 2.3 to 2.7 V
Location
6.0 ns max for 1.65 to 1.95 V
WL
= Wafer Lot
YY
= Year
Static Drive:
±24
mA Drive at 3.0 V
WW
= Work Week
±12
mA Drive at 2.3 V
±4
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
ORDERING INFORMATION
Logic State
Device
Package
Shipping
†
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
74ALVCH16244DTR TSSOP 2500/Tape & Reel
Near Zero Static Supply Current in All Three Logic States (40
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
±250
mA @ 125°C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16244
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to V
CC
through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 2
1
Publication Order Number:
74ALVCH16244/D
74ALVCH16244
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
V
CC
7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
V
CC
18
O12 19
O13 20
GND 21
O14 22
O15 23
OE4 24
48 OE2
47 D0
46 D1
45 GND
44 D2
43 D3
42 V
CC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 V
CC
30 D12
29 D13
28 GND
27 D14
26 D15
25 OE3
OE1
48
OE2
25
OE3
24
OE4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
1
1
OE1
OE2
1
48
OE3
OE4
25
24
D0:3
O0:3
D8:11
O8:11
D4:7
O4:7
D12:15
O12:15
One of Four
Figure 2. Logic Diagram
EN1
EN2
EN3
EN4
1
1
∇
2
3
5
6
8
9
11
2
∇
3
∇
12
13
14
16
Figure 1. 48−Lead Pinout
(Top View)
4
∇
17
19
20
22
23
PIN NAMES
Pins
OEn
D0−D15
O0−O15
Function
Output Enable Inputs
Inputs
Outputs
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
Figure 3. IEC Logic Diagram
OE1
L
L
H
D0:3
L
H
X
O0:3
L
H
Z
OE2
L
L
H
D4:7
L
H
X
O4:7
L
H
Z
OE3
L
L
H
D8:11
L
H
X
O8:11
L
H
Z
OE4
L
L
H
D12:15
L
H
X
O12:15
L
H
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for
I
CC
reasons, DO NOT FLOAT Inputs
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2
74ALVCH16244
MAXIMUM RATINGS
(Note 1)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30 to 35
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Above V
CC
and Below GND at 125°C (Note 6)
V
I
< GND
V
O
< GND
Parameter
Value
*0.5
to
)4.6
*0.5
to
)4.6
*0.5
to
)4.6
*50
*50
$50
$100
$100
*65
to
)150
260
)150
90
Level 1
UL 94 V−O @ 0.125 in
u2000
u200
N/A
$250
V
Unit
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
I
LATCH−UP
Latch−Up Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
V
CC
= 2.5 V
$
V
CC
= 3.0 V
$
0.2 V
0.3 V
Parameter
Operating
Data Retention Only
(Note 7)
(Active State)
(3−State)
Min
2.3
1.5
−0.5
0
0
*40
0
0
Max
3.6
3.6
3.6
3.6
3.6
)85
20
10
Unit
V
V
V
°C
ns/V
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
74ALVCH16244
DC ELECTRICAL CHARACTERISTICS
T
A
=
*405C
to
)855C
Symbol
V
IH
Parameter
HIGH Level Input Voltage
(Note 8)
1.65 V
v
V
CC
t
2.3 V
2.3 V
v
V
CC
v
2.7 V
2.7 V
t
V
CC
v
3.6 V
V
IL
LOW Level Input Voltage
(Note 8)
1.65 V
v
V
CC
t
2.3 V
2.3 V
v
V
CC
v
2.7 V
2.7 V
t
V
CC
v
3.6 V
V
OH
HIGH Level Output Voltage
1.65 V
v
V
CC
v
3.6 V; I
OH
=
*100
mA
V
CC
= 1.65 V; I
OH
=
*4
mA
V
CC
= 2.3 V; I
OH
=
*6
mA
V
CC
= 2.3 V; I
OH
=
*12
mA
V
CC
= 2.7 V; I
OH
=
*12
mA
V
CC
= 3.0 V; I
OH
=
*12
mA
V
CC
= 3.0 V; I
OH
=
*24
mA
V
OL
LOW Level Output Voltage
1.65 V
v
V
CC
v
3.6 V; I
OL
= 100
mA
V
CC
= 1.65 V; I
OL
= 4 mA
V
CC
= 2.3 V; I
OL
= 6 mA
V
CC
= 2.3 V; I
OL
= 12 mA
V
CC
= 2.7 V; I
OL
= 12 mA
V
CC
= 3.0 V; I
OL
= 24 mA
I
I
I
I(HOLD)
Input Leakage Current
Minimum Bus−hold Input
Current
1.65 V
v
V
CC
v
3.6 V; 0 V
v
V
I
v
3.6 V
V
CC
= 3.6 V; V
IN
= 0 to 3.6 V
V
CC
= 3.0 V, V
IN
= 0.8 V
V
CC
= 3.0 V, V
IN
= 2.0 V
V
CC
= 2.3 V, V
IN
= 0.7 V
V
CC
= 2.3 V, V
IN
= 1.7 V
V
CC
= 1.65 V, V
IN
= 0.58 V
V
CC
= 1.65 V, V
IN
= 1.07 V
I
OZ
I
OFF
I
CC
3−State Output Current
Power−Off Leakage Current
Quiescent Supply Current
(Note 9)
Increase in I
CC
per Input
1.65 V
v
V
CC
v
3.6 V; 0 V
v
V
O
v
3.6 V; V
I
= V
IH
or V
IL
V
CC
= 0 V; V
I
or V
O
= 3.6 V
1.65 V
v
V
CC
v
3.6 V; V
I
= GND or V
CC
1.65 V
v
V
CC
v
3.6 V; 3.6 V
v
V
I
, V
O
v
3.6 V
2.7 V
t
V
CC
≤
3.6 V; V
IH
= V
CC
*
0.6 V
75
*75
45
*45
25
*25
$10
10
40
$40
750
mA
mA
mA
mA
V
CC
*
0.2
1.20
2.0
1.7
2.2
2.4
2.0
0.2
0.45
0.4
0.7
0.4
0.55
$5.0
$500
mA
mA
V
Condition
0.65
1.7
2.0
0.35
0.7
0.8
V
V
CC
V
Min
V
CC
Max
Unit
V
DI
CC
8. These values of V
I
are used to test DC electrical characteristics only.
9. Outputs disabled or 3−state only.
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4
74ALVCH16244
AC CHARACTERISTICS
(Note 10; t
R
= t
F
= 2.0 ns; C
L
= 30 pF; R
L
= 500
W)
Limits
T
A
=
−40°C
to +85°C
V
CC
= 3.0 V to 3.6 V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Parameter
Propagation Delay
Input to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Output−to−Output Skew
(Note 11)
Waveform
1
2
2
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
3.0
3.0
4.4
4.4
4.1
4.1
0.5
0.5
V
CC
= 2.3 V to 2.7 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
3.7
3.7
5.7
5.7
5.2
5.2
0.5
0.5
V
CC
= 1.65 V
−
1.95 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
6.0
6.0
8.2
8.2
6.8
6.8
0.75
0.75
Unit
ns
ns
ns
ns
10. For C
L
= 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Condition
Note 12
Note 12
Note 12, 10 MHz
Typical
6
7
20
Unit
pF
pF
pF
12. V
CC
= 1.8, 2.5 or 3.3 V; V
I
= 0 4 V or V
CC
.
V
IH
Dn
V
m
t
PLH
On
V
m
WAVEFORM 1 − PROPAGATION DELAYS
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
V
IH
OEn
t
PZH
On
V
m
t
PHZ
V
m
0V
V
OH
V
y
≈
0V
t
PZL
On
V
m
V
x
V
OL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
t
PLZ
≈
V
CC
V
m
0V
t
PHL
V
m
V
OL
V
OH
Figure 4. AC Waveforms
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