INTEGRATED CIRCUITS
74ABT16652
74ABTH16652
16-bit transceiver/register, non-inverting
(3-State)
Product specification
Supersedes data of 1995 Aug 17
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit transceiver/register, non-inverting (3-State)
74ABT16652
74ABTH16652
FEATURES
•
Independent registers for A and B buses
•
Multiple V
CC
and GND pins minimize switching noise
•
Power-up 3-State
•
74ABTH16652 incorporates bus-hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
DESCRIPTION
The 74ABT16652 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16652 transceiver/register consists of two sets of bus
transceiver circuits with 3-State outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes HIGH. Output Enable (nOEAB, (nOEBA) and Select (nSAB,
nSBA) pins are provided for bus management.
Two options are available, 74ABT16652 which does not have the
bus-hold feature and 74ABTH16652 which incorporates the
bus-hold feature.
•
Power-up reset
•
Live insertion/extraction permitted
•
Multiplexed real-time and stored data
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
I
CCL
PARAMETER
Propagation delay nAx to nBx
Input capacitance
I/O capacitance
Quiescent supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
=5.5V
Outputs low; V
CC
= 5.5V
TYPICAL
2.3
1.8
4
7
500
8
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16652 DL
74ABT16652 DGG
74ABTH16652 DL
74ABTH16652 DGG
NORTH AMERICA
BT16652 DL
BT16652 DGG
BH16652 DL
BH16652 DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
LOGIC SYMBOL
1 56
28 29
1OEAB
1OEBA
2OEAB
14
13
12
10
9
8
6
5
1A7
1A6
1A5
1A4
1A3
1A2
1B7
1B6
1B5
1B4
1B3
1B2
1CPBA
43
44
45
47
48
49
51
52
24
23
21
20
19
17
16
15
2OEBA
2A7
2A6
2A5
2A4
2A3
2A2
2B7
2B6
2B5
2B4
2B3
2B2
2CPBA
33
34
36
37
38
40
41
42
1CPAB
2CPAB
1A1
1A0
1B1
1B0
2A1
2A0
2B1
2B0
1SAB
1SBA
2SAB
2
3 54 55
27 26 31 30
2SBA
SH00047
1998 Feb 27
2
853-1790 19026
Philips Semiconductors
Product specification
16-bit transceiver/register, non-inverting (3-State)
74ABT16652
74ABTH16652
PIN CONFIGURATION
1OEAB
1CPAB
1SAB
GND
1A0
1A1
V
CC
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2SAB
2CPAB
20EAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1CPBA
1SBA
GND
1B0
1B1
V
CC
1B2
1B3
1B4
GND
1B5
1B6
1B7
2B0
2B1
2B2
GND
2B3
2B4
2B5
V
CC
2B6
2B7
GND
2SBA
2CPBA
2OEBA
LOGIC SYMBOL (IEEE/IEC)
1OEBA 56
1OEAB 1
1CPBA 55
1SBA 54
1CPAB 2
1SAB 3
2OEBA 29
2OEAB 28
2CPBA 30
2SBA 31
2CPAB 27
2SAB 26
EN1 [BA]
EN2 [AB]
C3
G4
C5
G6
EN7 [BA]
EN8 [AB]
C9
G10
C11
G12
w1
∇1
5D
1
1A1
1A2
1A3
6
8
9
6
6
51 1B1
49 1B2
48 1B3
47 1B4
45 1B5
44 1B6
43 1B7
∇7
w1
10
10
12
12
41 2B1
40 2B2
38 2B3
37 2B4
36 2B5
34 2B6
33 2B7
9D
1
w1
8∇
42 2B0
52 1B0
1AO
5
4
4 1
w1
3D
2∇
1A4 10
1A5 12
1A6 13
1A7 14
2A0 15
11D
1
2A1 16
2A2 17
2A3 19
2A4 20
2A5 21
2A6 23
2A7 24
SH00046
SH00045
PIN DESCRIPTION
PIN NUMBER
2, 55, 27, 30
3, 54, 26, 31
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
1, 56, 28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1CPAB, 1CPBA, 2CPAB, 2CPBA
1SAB, 1SBA, 2SAB, 2SBA
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
1OEAB, 1OEBA,
2OEAB, 2OEBA
GND
V
CC
NAME AND FUNCTION
Clock input A to B / Clock input B to A
Select input A to B / Select input B to A
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Output enable inputs
Ground (0V)
Positive supply voltage
1998 Feb 27
3
Philips Semiconductors
Product specification
16-bit transceiver/register, non-inverting (3-State)
74ABT16652
74ABTH16652
LOGIC DIAGRAM
nOEBA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
1of 8 Channels
1D
C1
Q
nA0
1D
C1
Q
nB0
nA1
nA2
nA3
nA4
nA5
nA6
nA7
DETAIL A X 7
nB1
nB2
nB3
nB4
nB5
nB6
nB7
SH00065
FUNCTION TABLE
INPUTS
nOEAB
L
L
X
H
L
L
L
L
H
H
H
H
L
X
↑
*
**
=
=
=
=
nOEBA
H
H
H
H
X
L
L
L
H
H
L
nCPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
nCPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
nSAB
X
X
X
**
X
X
X
X
L
H
H
nSB
A
X
X
X
X
X
**
L
H
X
X
H
nAx
Input
Input
Unspecified
output*
Output
Input
Output
DATA I/O
nBx
Input
Unspecified
output*
Input
Input
Output
Output
Isolation
Store A and B data
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Store A data to B bus
Stored A data to B bus
Stored B data to A bus
OPERATING MODE
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must
be staggered in order to load both registers.
1998 Feb 27
4
Philips Semiconductors
Product specification
16-bit transceiver/register, non-inverting (3-State)
74ABT16652
74ABTH16652
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT16652.The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
A
B
A
B
A
B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
L
L
X
X
X
L
}
A
1998 Feb 27
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
H
H
X
X
L
X
TRANSFER STORED DATA
TO A OR B
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
H
L
H|L
H|L
H
H
}
L
L
X
H
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
X
H
↑
X
X
X
X
↑
↑
↑
X
X
X
X
}
B
}
SH00066
5
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