SM5160CM/DM
NIPPON PRECISION CIRCUITS INC.
Programable PLL Frequency Synthesizer
OVERVIEW
The SM5160CM/DM is a PLL frequency synthesizer
IC with programmable input and reference frequency
dividers.
The SM5160CM/DM features an unlock detector, out-
puts for use with active passive lowpass filters and direct
frequency divider outputs.
The SM5160CM/DM operates from 0.95 to 2.00 V
and 2.0 to 3.3 V supplies and is available in 16-pin
SSOPs.
PINOUT
(Top View)
XIN
XOUT
VDD3
DOA
DOP
VSS
FIN
VDD1
1
16
TEST
FR
FV
LE
DATA
CLK
LD
16 0
8
9
VDD2
FEATURES
• Up to 95 MHz input frequency (FIN, V
DD
= 0.98V)
• Up to 90 MHz input frequency (FIN, V
DD
= 0.95V)
• Up to 13.0 MHz reference frequency (XIN)
• 1056 to 65535 programmable input frequency
divider ratio
• 20 to 65532 programmable reference frequency
divider ratio (SM5160CM)
• 20 to 8188 programmable reference frequency
divider ratio (SM5160DM)
• Unlock detector
• Outputs for use with active and passive lowpass
filters
• Direct outputs from frequency dividers
• 0.95 to 2.0 V and 2.0 to 3.3 V supplies
• Molybdenum- gate CMOS process
• 16-pin SSOP
PACKAGE DIMENSIONS
(Unit: mm)
4.4 0.2
6.2 0.3
0.6TYP
6.8 0.3
0.15
- 0.05
+ 0.10
0.05 0.05
1.5 0.1
0.36 0.1
0.8
0 10
0.4 0.2
SERIES LINEUP
XIN
SM5160CM
SM5160DM
Divider range
Counter bits
Divider range
Counter bits
20 to 65532 (4 step)
14 bit
20 to 8188 (4 step)
11 bit
FIN
1056 to 65535
16 bit
1056 to 65535
16 bit
NIPPON PRECISION CIRCUITS-1
SM5160CM/DM
BLOCK DIAGRAM
VDD1
VDD2
1/4
PRESCALER
XIN
XOUT
TEST
DATA
CLK
11 or 14 BIT
R COUNTER
FR
LEVEL
SHIFTER
LD
LOCK
DETECTOR
14 BIT LATCH
17 BIT SHIFT REGISTER
PHASE
DETECTOR
VDD3
LE
FIN
VDD1
16 BIT LATCH
CHARGE
PUMP
DOA
DOP
16 BIT N COUNTER
LEVEL
SHIFTER
VDD2
FV
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
XIN
XOUT
VDD3
DOA
DOP
VSS
FIN
VDD1
VDD2
LD
CLK
DATA
LE
FV
FR
TEST
Description
Reference oscillator or external clock input. Internal feedback resistor for AC coupling
Reference oscillator or external clock output. Oscillator is OFF when VDD1 is LOW.
Supply voltage for sections not supplied by VDD1 and VDD2
Output to active lowpass filter. Single-ended, tristate output. Floating when VDD1 is LOW
Output to passive lowpass filter. Single-ended, tristate output Floating when VDD1 is LOW
Ground
Comparison frequency input. Internal feedback resistor for AC coupling
Supply voltage for XIN and FIN amplifiers
Supply voltage for N counter and R counter
Unlock detector output. LOW when PLL is unlocked.
Shift register clock input
Serial data input
Latch enable input
Input frequency divider buffered output. This is level-shifted and input to the phase detector.
Reference frequency divider buffered output. This is level-shifted and input to the phase detector.
Test input. Internal pull-down resistor
NIPPON PRECISION CIRCUITS-2
SM5160CM/DM
SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Supply voltage range 1
Supply voltage range 2
Input voltage range
Operating temperature range
Storage temperature range
Soldering temperature range
Soldering time range
Symbol
V
DD1
−V
SS
V
DD2
−V
SS
V
DD3
-V
SS
V
IN
T
OPR
T
STG
T
SLD
−0.3
to
+7.0
V
SS
−0.3
to V
DD
+0.3
−10
to
+60
−40
to
+125
250
10
V
V
°C
°C
°C
sec
Condition
Rating
−0.3
to
+7.0
Unit
V
t
SLD
Electrical Characteristics
(V
DD1
= V
DD2
= 0.95 to 2.0V, V
DD3
= 2.0 to 3.3V, V
SS
= 0V, Ta=
−10
to +60
°C
unless otherwise noted)
Rating
Parameter
Supply voltage 1
Supply voltage 2
Symbol
V
DD1
,V
DD2
V
DD3
Condition
VDD1 and VDD2 pins
VDD3 pin
F
IN
= 90MHz, 0.5V
P-P
sine wave
X
IN
= 12.8MHz, 0.5V
P-P
sine wave
Current consumption
(*1)
I
DD1
V
DD1
= V
DD2
= 0.95 to 1.05V
F
IN
= 95MHz, 0.5V
P-P
sine wave
X
IN
= 12.8MHz, 0.5V
P-P
sine wave
V
DD1
= V
DD2
= 0.98 to 1.08V
Standby-mode current consumption
FIN maximum operating frequency
I
DD2
f
MAX1
V
DD1
= V
DD2
= 0V
F
IN
: 0.5V
P-P
sine wave
V
DD1
= V
DD2
= 0.95 to 2.0V
F
IN
: 0.5V
P-P
sine wave
V
DD1
= V
DD2
= 0.98 to 2.0V
XIN maximum operating frequency
FIN minimum operating frequency
XIN minimum operating frequency
FIN and XIN input voltage
CLK, DATA and LE
input voltage
XIN input current
FIN input current
DOA and DOP
output current
LD, FV and FR
output current
DATA to CLK and CLK to LE
setup time
hold time
*1
f
MAX2
f
MIN1
f
MIN2
V
IN
V
IH
V
IL
I
IH1
I
IL1
I
IH2
I
IL2
I
OH1
I
OL1
I
OH1
I
OL1
V
IH
= V
DD1
V
IL
= 0V
V
IH
= V
DD1
V
IL
= 0V
V
DD3
= 2.7 to 3.3V, V
OH
= V
DD3
−
0.4V
V
DD3
= 2.7 to 3.3V, V
OL
= 0.4V
V
OH
= V
DD2
−
0.4V
V
OH
= 0.4V
1.0
1.0
0.1
0.1
2
2
2
X
IN
: 0.5V
P-P
sine wave
F
IN
: 0.5V
P-P
sine wave
X
IN
: 0.5V
P-P
sine wave
FIN and XIN pins
0.5
V
DD3
−
0.3
0.3
10
10
60
60
13
40
7
V
DD1
MHz
MHz
MHz
V
P-P
V
V
µA
µA
µA
µA
mA
mA
mA
mA
µs
µs
µs
95
MHz
90
10
µA
MHz
0.85
1.40
mA
0.80
1.20
mA
min
0.95
2.0
typ
1.00
3.0
max
2.0
3.3
Unit
V
V
t
SU1
t
SU2
t
H
Current consumption is the current consumed from V
DD1
and V
DD2
.
NIPPON PRECISION CIRCUITS-3
SM5160CM/DM
Serial data input timing
DATA
50%
50%
t
SU1
CLK
50%
t
H
LE
t
SU2
50%
Phase detector timing
FR
FV
DOP
DOA
LD
NIPPON PRECISION CIRCUITS-4
SM5160CM/DM
FUNCTIONAL DESCRIPTION
Lowpass Filter Connection
An external lowpass filter connects to DOP or DOA.
The output form the filter is fed to a voltage-controlled
oscillator (VCO) which generates the PLL output.
DOP is intended for use with a passive filter as shown
in figure 1. DOA is intended for use with an active filter
as shown in figure 2.
Programmable Frequency Divider
The input frequency divider and reference frequency
divider ratios can be programmed using the serial data
input.
Input data consists of 16 data bits, in the order msb to
lsb, followed by a control bit, as shown in figure 3 and 4.
SM5160CM
If the control bit is set to 0, the data is written to the
16-bit latch and then passed to the input frequency
divider.
If the control bit is set to 1, the 2 lsbs are ignored and
the remaining data is written to the 14-bit latch and then
passed to the reference frequency divider.
R1
DOP
R2
C
VCO
16BIT (N- COUNTER DATA)
CONTROL
Figure 1. Passive lowpass filter circuit
ignored
14BIT (R- COUNTER DATA)
0: N-LATCH
V
DD
V
DD
1: R-LATCH
R2
R1
DOA
C
R
L
VCO
Figure 3. Serial data format (SM5160CM)
SM5160DM
If the control bit is set to 0, the data is written to the
16-bit latch and then passed to the input frequency
divider.
If the control bit is set to 1, the 2 lsbs and 3msbs are
ignored and the remaining data is written to the 11-bit
latch and then passed to the reference frequency divider.
510k
Ω
Figure 2. Active lowpass filter circuit
CONTROL
LSB
16BIT (N- COUNTER DATA)
ignored
11BIT (R- COUNTER DATA)
0: N-LATCH
ignored
1: R-LATCH
Figure 4. Serial data format (SM5160DM)
NIPPON PRECISION CIRCUITS-5
MSB
MSB
LSB
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