SM5165AV
NIPPON PRECISION CIRCUITS INC.
PLL Synthesizer IC
OVERVIEW
The SM5165AV is a PLL synthesizer IC developed
for application in pagers and fabricated using NPC’s
Molybdenum-gate CMOS process. It incorporates
independently-controlled reference frequency and
operating frequency dividers, and operates from a
low-voltage supply to realize low power dissipation.
PINOUT
(TOP VIEW)
16pin VSOP
VDD1
FIN
VSS
RO
TEST
DO
DB
NC
8
1
16
XIN
XOUT
LE
CLK
DATA
OPR
VDD2
5165AV
FEATURES
s
s
s
s
s
s
s
s
s
Up to 90 MHz operating frequency
(V
DD1
= V
DD2
= 0.95 V)
Up to 100 MHz operating frequency
(V
DD1
= V
DD2
= 1.00 V)
Supply voltages
• V
DD1
= V
DD2
= 0.95 to 1.5 V
(prescaler, counters)
• V
DD3
= 2.0 to 3.3 V (charge pump)
40 to 16376 reference frequency divider ratio
range (with 1/8 prescaler built-in)
1056 to 262143 operating frequency divider ratio
range
Power-save function for reduced power
dissipation
−10
to 60
°C
operating temperature range
16-pin VSOP
Molybdenum-gate CMOS process
9
VDD3
PACKAGE DIMENSIONS
Unit: mm
16-pin VSOP
4.4 0.2
6.4 0.2
APPLICATIONS
s
5.1 0.2
0.15
-
+ 0.10
0.05
Pagers
0 10
0.22
- 0.05
0.65
0.10 0.05
1.15 0.1
ORDERING INFOMATION
Device
SM5165AV
Package
16pin VSOP
+ 0.10
0.5 0.2
NIPPON PRECISION CIRCUITS—1
SM5165AV
BLOCK DIAGRAM
XIN
XOUT
VDD2
DATA
CLK
LE
OPR
LATCH
SELECTER
1/8
PRESCALER
VDD1
AREA
VDD2
AREA
11 BIT
R COUNTER
LEVEL
SHIFTER
VDD2
AREA
TEST
RO
11 BIT LATCH
VDD3
AREA
PHASE
DETECTOR
VDD3
22 BIT
SHIFT REGISTER
BOOSTER
S. G.
DB
∗
VDD1
AREA
18 BIT LATCH
CHARGE
PUMP
DO
VDD1
FIN
LEVEL
SHIFTER
LEVEL
SHIFTER
18 BIT
N COUNTER
VDD2
AREA
VSS
WINDOW
GENERATOR
∗Protection
diodes are connected to VDD3. Logic level : V
DD2
to V
DD3
PIN DESCRIPTION
Number
1
2
3
4
5
Name
VDD1
FIN
VSS1
RO
TEST
I/O
–
I
–
O
I
Description
Reference frequency and comparator frequency prescaler and counter 1 V supply
Operating frequency divider input pin.
Feedback resistor built-in for AC-coupled inputs.
Ground pin
Test output.
LOW-level output for (1, 0) test bit patter. Leave open for normal operation.
Test pin.
Pull-down resistor built-in. Leave open or connect to ground for normal operation.
Phase detector output pin.
Built-in charge pump and tristate output means that this output can be connected to a low-pass filter.
The output polarity is preset for connection to a passive filter.
Booster signal output for faster locking
No connection
Phase comparator, charge pump and booster signal 3 V supply
Shift register and latch 1 V supply.
Should be kept at the same potential as VDD1.
Power-save control pin.
Operation when HIGH, standby mode when LOW.
Control data input pin
Control data clock input pin
Control data latch enable signal input pin
Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can
be connected to XIN. The clock is also output on XOUT.
Feedback resistor built-in for AC-coupled inputs.
6
7
8
9
10
11
12
13
14
15
16
DO
DB
NC
VDD3
VDD2
OPR
DATA
CLK
LE
XOUT
XIN
O
O
–
–
–
I
I
I
I
O
I
NIPPON PRECISION CIRCUITS—2
SM5165AV
SPECIFICATIONS
Absolute Maximum Ratings
V
SS
= 0 V
Parameter
Supply voltage
Symbol
V
DD1,2
V
DD3
Input voltage range
Storage temperature range
Power dissipation
Soldering temperature
Soldering time
V
IN1
V
IN2
T
stg
P
D
T
sld
t
sld
FIN, XIN, TEST
OPR, CLK, DATA, LE
Condition
Rating
−0.3
to 2.0
−0.3
to 7.0
V
SS
−
0.3 to V
DD1,2
+ 0.3
V
SS
−
0.3 to V
DD3
+ 0.3
−40
to 125
150
255
10
Unit
V
V
V
V
°C
mW
°C
s
Recommended Operating Conditions
V
SS
= 0 V
Parameter
Supply voltage
Storage temperature range
Symbol
V
DD1,2
V
DD3
T
stg
Condition
Rating
0.95 to 1.5
2.0 to 3.3
−10
to 60
Unit
V
V
°C
Electrical Characteristics
V
SS
= 0 V, V
DD1
= V
DD2
= 0.95 to 1.5 V, V
DD3
= 2.0 to 3.3 V, T
a
=
−10
to 60
°C
Rating
Parameter
VDD1, VDD2 operating current
consumption
VDD3 operating current consumption
VDD2 standby current
VDD3 standby current
Symbol
Note 1.
I
DD1
I
DD2
I
DD3
I
DD4
300 mVp-p sine
wave
V
DD1,2
= 0.95 to
1.50 V
V
DD1,2
= 1.00 to
1.50 V
Note 3.
–
90
100
16
–
–
0.3
0.3
0.3
–
0.01
–
–
–
–
–
–
–
–
–
10.0
–
MHz
–
–
40
9
–
Vp-p
V
DD1,2
= 1.00 to 1.50 V, f
FIN
= 100 MHz,
AC coupling
f
XIN
= 16 MHz, AC coupling
–
–
0.2V
DD2
Vp-p
V
MHz
MHz
MHz
µA
Note 2.
Condition
min
–
–
–
–
typ
0.70
0.75
10
0.1
max
1.10
mA
1.20
–
–
µA
µA
Unit
FIN maximum operating input frequency
f
max1
XIN maximum operating input frequency
FIN minimum operating input frequency
XIN minimum operating input frequency
f
max2
f
min1
f
min2
300 mVp-p sine wave. Note 4.
300 mVp-p sine wave
300 mVp-p sine wave. Note 4.
V
DD1,2
= 0.95 to 1.50 V, f
FIN
= 90 MHz,
AC coupling
FIN input amplitude
V
FIN
XIN input amplitude
OPR, CLK, DATA, LE LOW-level input
voltage
V
XIN
V
IL
NIPPON PRECISION CIRCUITS—3
SM5165AV
Rating
Parameter
OPR, CLK, DATA, LE HIGH-level input
voltage
FIN LOW-level input current
XIN LOW-level input current
FIN HIGH-level input current
XIN HIGH-level input current
DO, DB LOW-level output current
DO, DB HIGH-level output current
Tristate output high-impedance leakage
current
DATA
→
CLK setup time
CLK
→
LE setup time
Hold time
Symbol
Condition
min
V
IH
I
IL1
I
IL2
I
IH1
I
IH2
I
OL
I
OH
I
OZL
I
OZH
t
SU1
t
SU2
t
H
Note 7.
V
IL
= 0 V
0.8V
DD2
–
–
–
V
IH
= V
DD1
Note 5.
Note 6.
V
OL
= 0 V
V
OH
= V
DD3
–
1.0
1.0
–
–
2
2
2
typ
–
–
–
–
–
–
–
–
–
–
–
–
max
V
DD3
60
10
60
10
–
–
100
100
–
–
–
V
µA
µA
µA
µA
mA
mA
nA
nA
µs
µs
µs
Unit
1. V
DD1
= V
DD2
= 0.95 to 1.05 V, V
DD3
= 2.7 to 3.3 V, f
FIN
= 90 MHz (300 mVp-p sine wave), f
XIN
= 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no
output load
2. V
DD1
= V
DD2
= 1.00 to 1.05 V, V
DD3
= 2.7 to 3.3 V, f
FIN
= 100 MHz (300 mVp-p sine wave), f
XIN
= 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no
output load
3. V
DD1
= 0 V, V
DD2
= 0.95 to 1.05 V, V
DD3
= 2.7 to 3.3 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V)
4. Externally-input sine wave
5. DO and DB outputs are derived from the V
DD3
supply. V
DD3
= 2.7 to 3.3 V, V
OL
= 0.4 V
6. DO and DB outputs are derived from the V
DD3
supply. V
DD3
= 2.7 to 3.3 V, V
OH
= V
DD3
−
0.4 V
7. Setup and hold times.
DATA
CLK
LE
V
IH
t
SU1
V
IH
t
SU2
V
IH
t
H
V
IH
NIPPON PRECISION CIRCUITS—4
SM5165AV
FUNCTIONAL DESCRIPTION
Operating Frequency Divider
(N-counter) Structure
The operating frequency divider generates a compar-
ator frequency signal (FV), which is input to the
phase comparator, by dividing the VCO signal input
on pin FIN.
The operating frequency divider is comprised by
dual modulus prescalers, a 5-bit swallow counter and
a 13-bit main counter.
The settings for the dual modulus prescaler (P and P
+ 1), swallow counter (S) and main counter (M) are
related to the comparator frequency divider ratio by:
N =
(
P + 1
) ×
S + P
(
M – S
)
= PM + S
The counter value ranges are P = 32, P + 1 = 33, S =
0 to 31, and M = 32 to 8191. Therefore, the compara-
tor frequency divider ratio range N is 1056 to
262143.
The settings for the prescaler (A = 8) and reference
counter (R) are related to the reference frequency
divider ratio by:
R = AB = 8B
The counter value ranges are A = 8 and B = 5 to
2047. Therefore, the reference frequency divider
ratio range is R = 40 to 16376.
Input Data
The input data should be specified keeping in mind
both the V
DD2
and V
DD3
supplies. The data is input
using CLK, DATA and LE pins into the shift register
and latch which operate from the V
DD2
supply. How-
ever, the input voltages can be specified using either
the V
DD2
or V
DD3
supply levels.
The control data input uses a 3-line 23-bit serial
interface comprising the clock (CLK), data input
(DATA) and latch enable (LE). The data is input with
the MSB first. The last (23rd) bit is used as the latch
select control bit. Data is written to the shift register
on the rising edge of the clock signal. Accordingly,
the data should change state on the falling edge of
the clock signal. Data is transferred from the shift
register to the latch when the latch enable (LE) sig-
nal goes HIGH. Accordingly, the latch enable signal
should be held LOW while data is being written to
the shift register.
The clock and data input signals are both ignored
when the latch enable signal goes HIGH.
Reference Frequency Divider
(R-counter) Structure
The reference frequency divider generates a compar-
ator frequency signal (FR), which is input to the
phase comparator, by dividing the reference oscilla-
tor frequency input either from an external signal on
XIN or from a crystal oscillator connected between
XIN and XOUT.
The reference frequency divider is comprised by a
fixed divide-by-8 prescaler and an 11-bit reference
counter.
Input data format
CLK
DATA
LE
1
MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LSB
CONTROL
NIPPON PRECISION CIRCUITS—5
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