Philips Semiconductors
Product specification
Thyristors
logic level
GENERAL DESCRIPTION
Glass passivated, sensitive gate
thyristors in a plastic envelope,
intended for use in general purpose
switching
and
phase
control
applications. These devices are
intended to be interfaced directly to
microcontrollers, logic integrated
circuits and other low power gate
trigger circuits.
BT148 series
QUICK REFERENCE DATA
SYMBOL
V
DRM
,
V
RRM
I
T(AV)
I
T(RMS)
I
TSM
PARAMETER
BT148-
Repetitive peak off-state
voltages
Average on-state current
RMS on-state current
Non-repetitive peak on-state
current
MAX. MAX. MAX. UNIT
400R
400
2.5
4
35
500R
500
2.5
4
35
600R
600
2.5
4
35
V
A
A
A
PINNING - SOT82
PIN
1
2
3
tab
DESCRIPTION
cathode
anode
gate
anode
PIN CONFIGURATION
SYMBOL
a
k
1
2
3
g
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
-
half sine wave; T
mb
≤
113 ˚C
all conduction angles
half sine wave; T
j
= 25 ˚C prior to
surge
t = 10 ms
t = 8.3 ms
t = 10 ms
I
TM
= 10 A; I
G
= 50 mA;
dI
G
/dt = 50 mA/µs
-
-
-
-
-
-
-
-
-
-
-
-40
-
MAX.
-400R -500R -600R
400
1
500
1
600
1
2.5
4
35
38
6.1
50
2
5
5
5
0.5
150
125
2
UNIT
V
A
A
A
A
A
2
s
A/µs
A
V
V
W
W
˚C
˚C
V
DRM
, V
RRM
Repetitive peak off-state
voltages
I
T(AV)
I
T(RMS)
I
TSM
Average on-state current
RMS on-state current
Non-repetitive peak
on-state current
I
2
t
dI
T
/dt
I
GM
V
GM
V
RGM
P
GM
P
G(AV)
T
stg
T
j
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
Peak gate current
Peak gate voltage
Peak reverse gate voltage
Peak gate power
Average gate power
over any 20 ms period
Storage temperature
Operating junction
temperature
1
Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor may
switch to the on-state. The rate of rise of current should not exceed 15 A/µs.
2
Note: Operation above 110˚C may require the use of a gate to cathode resistor of 1kΩ or less.
October 1997
1
Rev 1.300
Philips Semiconductors
Product specification
Thyristors
logic level
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
CONDITIONS
MIN.
-
-
BT148 series
TYP.
-
95
MAX.
2.5
-
UNIT
K/W
K/W
Thermal resistance
junction to mounting base
Thermal resistance
in free air
junction to ambient
STATIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
I
GT
I
L
I
H
V
T
V
GT
I
D
, I
R
PARAMETER
Gate trigger current
Latching current
Holding current
On-state voltage
Gate trigger voltage
Off-state leakage current
CONDITIONS
V
D
= 12 V; I
T
= 0.1 A
V
D
= 12 V; I
GT
= 0.1 A
V
D
= 12 V; I
GT
= 0.1 A
I
T
= 5 A
V
D
= 12 V; I
T
= 0.1 A
V
D
= V
DRM(max)
; I
T
= 0.1 A; T
j
= 110 ˚C
V
D
= V
DRM(max)
; V
R
= V
RRM(max)
; T
j
= 125 ˚C
MIN.
-
-
-
-
-
0.1
-
TYP.
15
0.17
0.10
1.23
0.4
0.2
0.1
MAX.
200
10
6
1.8
1.5
-
0.5
UNIT
µA
mA
mA
V
V
V
mA
DYNAMIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
dV
D
/dt
t
gt
t
q
PARAMETER
Critical rate of rise of
off-state voltage
Gate controlled turn-on
time
Circuit commutated
turn-off time
CONDITIONS
V
DM
= 67% V
DRM(max)
; T
j
= 125 ˚C;
exponential waveform; R
GK
= 100
Ω
I
TM
= 10 A; V
D
= V
DRM(max)
; I
G
= 5 mA;
dI
G
/dt = 0.2 A/µs
V
D
= 67% V
DRM(max)
; T
j
= 125 ˚C; I
TM
= 8 A;
V
R
= 10 V; dI
TM
/dt = 10 A/µs;
dV
D
/dt = 2 V/µs; R
GK
= 1 kΩ
MIN.
-
-
-
TYP.
50
2
100
MAX.
-
-
-
UNIT
V/µs
µs
µs
October 1997
2
Rev 1.300
Philips Semiconductors
Product specification
Thyristors
logic level
BT148 series
6
5
4
3
2
1
0
Ptot / W
conduction
angle
degrees
30
60
90
120
180
form
factor
BT148
a
4
2.8
2.2
1.9
1.57
Tmb(max) / C
ITSM / A
110
112.5
40
IT
I TSM
T
time
1.9
2.2
2.8
4
a = 1.57
115
117.5
120
30
Tj initial = 25 C max
20
10
122.5
125
3
0
0.5
1
1.5
IF(AV) / A
2
2.5
0
1
10
100
Number of half cycles at 50Hz
1000
Fig.1. Maximum on-state dissipation, P
tot
, versus
average on-state current, I
T(AV)
, where
a = form factor = I
T(RMS)
/ I
T(AV)
.
BT148
Fig.4. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
1000 ITSM / A
12
10
8
IT(RMS) / A
BT150
dI
T
/dt limit
100
ITSM
6
4
2
0
0.01
IT
time
T
Tj initial = 25 C max
10
10us
100us
T/s
1ms
10ms
0.1
1
surge duration / s
10
Fig.2. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus pulse width t
p
, for
sinusoidal currents, t
p
≤
10ms.
Fig.5. Maximum permissible repetitive rms on-state
current I
T(RMS)
, versus surge duration, for sinusoidal
currents, f = 50 Hz; T
mb
≤
113˚C.
VGT(Tj)
VGT(25 C)
5
IT(RMS) / A
BT148
1.6
113 C
BT151
4
1.4
1.2
1
3
2
0.8
1
0.6
0
50
Tmb / C
100
150
0
-50
0.4
-50
0
50
Tj / C
100
150
Fig.3. Maximum permissible rms current I
T(RMS)
,
versus mounting base temperature T
mb
.
Fig.6. Normalised gate trigger voltage
V
GT
(T
j
)/ V
GT
(25˚C), versus junction temperature T
j
.
October 1997
3
Rev 1.300
Philips Semiconductors
Product specification
Thyristors
logic level
BT148 series
3
2.5
2
1.5
1
0.5
IGT(Tj)
IGT(25 C)
BT148
12
10
IT / A
Tj = 125 C
Tj = 25 C
Vo = 1.26 V
Rs = 0.099 ohms
BT148
typ
max
8
6
4
2
0
0
-50
0
50
Tj / C
100
150
0
0.5
1
1.5
VT / V
2
2.5
3
Fig.7. Normalised gate trigger current
I
GT
(T
j
)/ I
GT
(25˚C), versus junction temperature T
j
.
IL(Tj)
IL(25 C)
Fig.10. Typical and maximum on-state characteristic.
3
2.5
BT145
10
Zth j-mb (K/W)
BT148
1
2
1.5
1
0.5
0
-50
0.01
10us
0.1ms
1ms
10ms
tp / s
0.1s
1s
0.1
P
D
tp
t
0
50
Tj / C
100
150
10s
Fig.8. Normalised latching current I
L
(T
j
)/ I
L
(25˚C),
versus junction temperature T
j
.
IH(Tj)
IH(25 C)
Fig.11. Transient thermal impedance Z
th j-mb
, versus
pulse width t
p
.
dVD/dt (V/us)
3
2.5
2
1.5
1
0.5
BT145
1000
RGK = 100 ohms
100
10
0
-50
0
50
Tj / C
100
150
1
0
50
Tj / C
100
150
Fig.9. Normalised holding current I
H
(T
j
)/ I
H
(25˚C),
versus junction temperature T
j
.
Fig.12. Typical, critical rate of rise of off-state voltage,
dV
D
/dt versus junction temperature T
j
.
October 1997
4
Rev 1.300
Philips Semiconductors
Product specification
Thyristors
logic level
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.8 g
BT148 series
mounting
base
2.8
2.3
7.8
max
3.75
3.1
2.5
11.1
max
1)
2.54
max
1.2
15.3
min
1
4.58
0.5
2
3
2.29
1) Lead dimensions within this
zone uncontrolled.
0.88
max
Fig.13. SOT82; pin 2 connected to mounting base.
Notes
1. Refer to mounting instructions for SOT82 envelopes.
2. Epoxy meets UL94 V0 at 1/8".
October 1997
5
Rev 1.300
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
