SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
8 - Bit Micro-controller
with 4/8KB flash embedded
Product List
SM8951A/8952AL25, 25 MHz 4/8KB internal memory MCU
SM8951A/8952AC25, 25 MHz 4/8KB internal memory MCU
SM8951A/8952AC40, 40 MHz 4/8KB internal memory MCU
Features
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8052 family compatible
12 clocks per machine cycle
4/8 KB internal flash memory
The SM8951A/8952A series product is an 8 - bit single chip
micro controller with 4/8 KB flash embedded. It provides hard-
ware features and a powerful instruction set, necessary to
make it a versatile and cost effective controller for those appli-
cations demand up to 32 I/O pins or need up to 4/8 KB flash
memory either for program or for data or mixed.
To program the flash block, a commercial programmer is
capable to do it.
Ordering Information
yywwv
SM8951A/8952Aihhk
yy: year, ww:week
v: version identifier {, A, B,...}
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Postfix
P
J
Q
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D
R
AF
T,
D
C
O
O
N NF
O
T ID
C EN
O
PY TIA
L
128/256 bytes data RAM
Four 8-bit I/O ports
2/3 16 bit timers/counters
Full duplex serial channel
Bit operation instruction
Page free jumps
8-bit unsigned division
BCD arithmetic
8-bit unsigned multiply
Direct addressing
Nested interrupt
A serial I/O port
Indirect addressing
Two priority level interrupt
Power save modes:
Idle mode and power down mode
Code protection function
One watch dog timer (WDT)
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Dimension
page 13
page 14
page 15
Description
Low EMI (inhibit ALE)
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-579-2926
886-3-579-2988
FAX: 886-3-579-2960
886-3-578-0493
1/17
Preliminary
Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
Pin Configurations
T2EX/P1.1
T2/P1.0
NC
VDD
P0.0/AD0
P0.1/AD1
T2EX/P1.1
T2/P1.0
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
D
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AF
T,
D
C
O
O
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O
T ID
C EN
O
PY TIA
L
6
5
P1.4
P1.3
P1.2
4
3
2
1 44 43 42 41 40
P1.5
7
39
P0.4/AD4
P0.5/AD5
P0.6/AD6
#EA/VPP
NC
ALE
#PSEN
P1.6
P1.7
RES
RXD/P3.0
NC
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
8
38
P1.5
P1.6
9
37
1
2
3
4
5
6
7
8
9
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
P0.2/AD2
P0.3/AD3
P1.4
P1.3
P1.2
NC
VDD
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA/VPP
NC
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
10
11
12
13
SM8951A/8952A
ihhJ
44L PLCC
36
P0.7/AD7
35
34
P1.7
RES
RXD/P3.0
33
14
(Top View)
15
16
17
18 19 20 21 22 23 24 25 26 27 28
32
NC
TXD/P3.1
#INT0/P3.2
SM8951A/8952A
ihhQ
44L QFP
(Top View)
31
30
P2.7/A15
P2.6/A14
P2.5/A13
29
#INT1/P3.3
T0/P3.4
T1/P3.5
10
11
12 13 14 15 16 17 18 19 20 21 22
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
P2.2/A10
P2.3/A11
P2.4/A12
P2.0/A8
P2.1/A9
NC
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
P2.3/A11
T2/P1.0
1
2
40
39
VDD
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA/VPP
ALE
3
4
5
38
37
36
6
7
35
34
8
33
RES
RXD/P3.0
TXD/P3.1
9
32
10
11
31
30
#INT/P3.2
12
13
29
#PSEN
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
28
27
26
25
24
23
22
21
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
14
15
16
17
18
19
20
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/17
Preliminary
Ver 0.2
P2.2/A10
PID 8951A/8952A 09/02
P2.4/A12
NC
P2.0/A8
P2.1/A9
SM8951A/8952A ihhP
40L PDIP
(Top View)
SyncMOS Technologies Inc.
September 2002
Block Diagram
Stack
Pointer
Preliminary
SM8951A/8952A
Timer 2
Timer 1
Timer 0
Decoder &
Register
128/256
bytes RAM
RES
Vdd
Vss
XTAL2
XTAL1
#EA
ALE
#PSEN
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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T,
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C EN
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PY TIA
L
WDT
Reset
Circuit
to pertinent blocks
Acc
Power
Circuit
to whole chip
Buffer2
Buffer1
Interrupt
Circuit
to pertinent blocks
ALU
PSW
to whole system
Timing
Generator
Instruction
Register
Port 0
Latch
Port 1
Latch
Port 2
Latch
Port 3
Latch
Port 0
Driver & Mux
8
Port 2
Port 3
Driver & Mux Driver & Mux Driver & Mux
8
8
8
Port 1
Buffer
DPTR
PC
Incrementer
Program
Counter
Register
4/8 K
bytes
Flash
Memory
3/17
Preliminary
Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Pin Descriptions
40L
PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
44L 44L
QFP PLCC
Symbol
Pin# Pin#
40
2
T2/P1.0
41
3
T2EX/P1.1
42
4
P1.2
43
5
P1.3
44
6
P1.4
1
7
P1.5
2
8
P1.6
3
9
P1.7
4
10 RES
5
11
RXD/P3.0
7
13 TXD/P3.1
8
14 #INT0/P3.2
9
15 #INT1/P3.3
10
16 T0/P3.4
11
17 T1/P3.5
12
18 #WR/P3.6
13
19 #RD/P3.7
14
20 XTAL2
15
21 XTAL1
16
22 VSS
18
24 P2.0/A8
19
25 P2.1/A9
20
26 P2.2/A10
21
27 P2.3/A11
22
28 P2.4/A12
23
29 P2.5/A13
24
30 P2.6/A14
25
31 P2.7/A15
26
32 #PSEN
27
33 ALE
29
35 #EA/VPP
30
36 P0.7/AD7
31
37 P0.6/AD6
32
38 P0.5/AD5
33
39 P0.4/AD4
34
40 P0.3/AD3
35
41 P0.2/AD2
36
42 P0.1/AD1
37
43 P0.0/AD0
38
44 VDD
I/O
Active
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
Names
Preliminary
SM8951A/8952A
H
L/ -
L/ -
L/ -
L/ -
L
-
L
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
timer 2 clock out & bit 0 of port 1
timer 2 control & bit 1 of port 1
bit 2 of port 1
bit 3 of port 1
bit 4 of port 1
bit 5 of port 1
bit 6 of port 1
bit 7 of port 1
Reset
Receive data & bit 0 of port 3
Transmit data & bit 1 of port 3
low true interrupt 0 & bit 2 of port 3
low true interrupt 1 & bit 3 of port 3
Timer 0 & bit 4 of port 3
Timer 1 & bit 5 of port 3
external memory write & bit 6 of port 3
external memory read & bit 7 of port 3
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of external memory address
bit 1 of port 2 & bit 9 of external memory address
bit 2 of port 2 & bit 10 of external memory address
bit 3 of port 2 & bit 11 of external memory address
bit 4 of port 2 & bit 12 of external memory address
bit 5 of port 2 & bit 13 of external memory address
bit 6 of port 2 & bit 14 of external memory address
bit 7 of port 2 & bit 15 of external memory address
program storage enable
address latch enable
external access & VPP
bit 7 of port 0 & data/address bit 7 of external memory
bit 6 of port 0 & data/address bit 6 of external memory
bit 5 of port 0 & data/address bit 5 of external memory
bit 4 of port 0 & data/address bit 4 of external memory
bit 3 of port 0 & data/address bit 3 of external memory
bit 2 of port 0 & data/address bit 2 of external memory
bit 1 of port 0 & data/address bit 1 of external memory
bit 0 of port 0 & data/address bit 0 of external memory
Drive Voltage, +5 Vcc
Specifications subject to change without notice,contact your sales representatives for the most recent information.
D
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AF
T,
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C
O
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N NF
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T ID
C EN
O
PY TIA
L
4/17
Preliminary
Ver 0.2
PID 8951A/8952A 09/02
SyncMOS Technologies Inc.
September 2002
Preliminary
SM8951A/8952A
SFR Memory MAP
$F8
$F0
$E8
$E0
$D8
$D0
$C8
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
B
ACC
$FF
$F7
$EF
$E7
$DF
$D7
$CF
SCONF
D
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T ID
C EN
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PY TIA
L
PSW
T2CON
IP
IE
RC2L
RC2H
TL2
TH2
P3
P2
P1
P0
SCON
TCON
SBUF
TMOD
SP
TL0
TL1
TH0
TH1
DPL
DPH
(Reserved)
5/17
Preliminary
Ver 0.2
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
WDTC
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8951A/8952A
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing
the WDT counter.
The SM8951A/8952A WDT has selectable divider input for the time base source clock. To select the divider input, the set-
ting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The
WDTE bit will be cleared to 0 automatically when SM8951A8952A been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
PID 8951A/8952A 09/02
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