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5962-9318704H4C

产品描述SRAM Module, 128KX32, 70ns, CMOS, HIP-66
产品类别存储    存储   
文件大小374KB,共34页
制造商Microsemi
官网地址https://www.microsemi.com
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5962-9318704H4C概述

SRAM Module, 128KX32, 70ns, CMOS, HIP-66

5962-9318704H4C规格参数

参数名称属性值
Objectid1820273715
零件包装代码PGA
包装说明HIP,
针数66
Reach Compliance Codecompliant
ECCN代码3A001.A.2.C
最长访问时间70 ns
其他特性USER CONFIGURABLE AS 512K X 8
备用内存宽度16
JESD-30 代码S-XHIP-P66
JESD-609代码e4
长度27.3 mm
内存密度4194304 bit
内存集成电路类型SRAM MODULE
内存宽度32
功能数量1
端子数量66
字数131072 words
字数代码128000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织128KX32
封装主体材料UNSPECIFIED
封装代码HIP
封装形状SQUARE
封装形式IN-LINE
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度4.95 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式PIN/PEG
端子节距2.54 mm
端子位置HEX
宽度27.3 mm

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REVISIONS
LTR
E
DESCRIPTION
Figure 1: For case outlines 4 and 5 changed the dimension D3 min
and max limits to 1.020 and 1.060 inches. For case outlines 4 and 5
changed dimension A min limit to .135 inches. For case outlines 4
and 5 changed dimension L min limit to .132 inches. -sld
Table I; changed the max limit for I
CC32
for device types 05, 06, 07,
and 08 from 520 mA to 600 mA. Changed the max limit for I
CCDR1
for
device types 05 through 10 from 10.4 mA to 11.6 mA. -sld
Added device type 11. Added vendor CAGE 0EU86 for device types
05 through 09. -sld
Figure 1; changed the maximum limit for dimension D3 from 1.060
inches to 1.086 inches for case outlines 4 and 5. -sld
Added note to paragraph 1.2.2 and table I regarding the 4 transistor
design. Added footnote 3 for case outlines U, T, X, and Y on the
bulletin page. Redrew entire document. -sld
Added device types 12 through 18. -sld
Updated drawing. -gz
Update drawing to the latest requirements of MIL-PRF-38534. –gc
DATE (YR-MO-DA)
98-04-06
APPROVED
K. A. Cottongim
F
98-07-13
K. A. Cottongim
G
H
J
99-08-27
00-02-07
00-11-14
Raymond Monnin
Raymond Monnin
Raymond Monnin
K
L
M
01-11-13
07-04-16
18-01-23
Raymond Monnin
Robert M. Heber
Charles F. Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
M
15
M
16
M
17
M
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
M
19
M
20
M
21
M
1
M
22
M
2
M
23
M
3
M
24
M
4
M
25
M
5
M
26
M
6
M
7
M
8
M
9
M
10
M
11
M
12
M
13
M
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.dla.mil/landandmaritime
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, DIGITAL, STATIC
RANDOM ACCESS MEMORY, CMOS, 128K x
32-BIT
DRAWING APPROVAL DATE
94-06-24
REVISION LEVEL
M
SIZE
A
SHEET
CAGE CODE
67268
1 OF
26
5962-93187
5962-E208-18
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

 
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