WS128K32V-XXX
128Kx32 3.3V SRAM MULTICHIP PACKAGE
FEATURES
s
Access Times of 15**, 17, 20, 25, 35ns
s
Low Voltage Operation
s
Packaging
• 66-pin, PGA Type, 1.075 inch square Hermetic Ceramic
HIP (Package 400)
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880 inch) square
(Package 509), 4.57mm (0.180 inch) high. Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2)
• 68 lead, Hermetic CQFP (G1U), 23.8mm (0.940 inch)
square (Package 509), 3.56mm (0.140 inch) high.
s
Organized as 128Kx32; User Configurable as 256Kx16 or
512Kx8
s
Commercial, Industrial and Military Temperature Ranges
PRELIMINARY*
s
3.3 Volt Power Supply
s
Low Power CMOS
s
TTL Compatible Inputs and Outputs
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight
WS128K32V-XG2TX - 8 grams typical
WS128K32V-XG1UX - 5 grams typical
WS128K32V-XH1X - 13 grams typical
*
This data sheet describes a product that is not fully qualified or
characterized and is subject ot change without notice.
** Commercial and Industrial temperature ranges only.
4
SRAM MODULES
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
11
PIN CONFIGURATION FOR WS128K32NV-XH1X
TOP VIEW
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
22
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
WE
1
CS
1
PIN DESCRIPTION
56
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
OE
A
0-16
I/O
23
I/O
22
128K x 8
128K x 8
128K x 8
128K x 8
I/O
21
I/O
20
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
8
8
8
8
April 2001 Rev. 2
1
White Microelectronics • (602) 437-1520 • www.whiteedc.com
WS128K32V-XXX
FIG. 2
PIN CONFIGURATION FOR WS128K32V-XG2TX AND WS128K32V-XG1UX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-16
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
WE
2
WE
3
WE
4
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
OE
NC
4
SRAM MODULES
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CS
2
NC
NC
NC
WE
1-4
CS
1-4
OE
V
CC
GND
NC
BLOCK DIAGRAM
WE
1
CS
1
OE
A
0-16
128K x 8
128K x 8
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
128K x 8
128K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WS128K32V-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
4.6
150
5.5
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
X
H
L
H
TRUTH TABLE
WE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
3.0
2.2
-0.3
Max
3.6
V
CC
+ 0.3
+0.8
Unit
V
V
V
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G2T/G1U
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
4
SRAM MODULES
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 3.3V
±0.3V,
V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current (x 32 Mode)
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
x 32
I
SB
V
OL
V
OH
Conditions
Min
V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz
CS = V
IH
, OE = V
IH
, f = 5MHz
I
OL
= 8mA
I
OH
= -4.0mA
2.4
Max
10
10
500
32
0.4
Units
µA
µA
mA
mA
V
V
3
White Microelectronics • (602) 437-1520 • www.whiteedc.com
WS128K32V-XXX
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
1
Symbol
-15*
Min
15
15
0
15
10
5
5
8
8
5
5
0
Max
-17
Min
17
17
0
17
11
5
5
9
9
Max
-20
Min
20
20
0
20
12
5
5
10
10
Max
Min
25
-25
Max
-35
Min
35
25
0
25
15
5
5
12
12
15
15
35
20
35
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
t
OHZ
1
4
SRAM MODULES
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
Symbol
-15*
Min
15
13
13
10
13
0
0
5
8
0
0
Max
-17
Min
17
14
14
11
14
0
0
5
9
0
Max
-20
Min
20
15
15
12
15
0
0
5
10
0
Max
-25
Min
25
20
20
15
20
0
0
5
10
0
Max
-35
Min
35
30
30
18
30
0
0
5
15
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WHZ
t
DH
1
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
FIG. 3
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WS128K32V-XXX
FIG. 4
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
RC
t
AA
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
FIG. 5
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
4
SRAM MODULES
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 6
WRITE CYCLE - CS CONTROLLED
ADDRESS
t
WC
WS32K32-XHX
t
AS
t
AW
t
CW
t
AH
CS
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
5
White Microelectronics • (602) 437-1520 • www.whiteedc.com
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