VSC8601
10/100/1000BASE-T PHY with RGMII
MAC Interface
Datasheet
VMDS-10210
Revision 4.1
September 2009
Vitesse
Corporate Headquarters
741 Calle Plano
Camarillo, California 93012
United States
www.vitesse.com
Copyright© 2005–2007, 2009 by Vitesse Semiconductor Corporation
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its
products or specifications to improve performance, reliability or manufacturability. All
information in this document, including descriptions of features, functions,
performance, technical specifications and availability, is subject to change without
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Safety of Laser Products, IEC 60825. While Vitesse products support IEC 60825, use of
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VSC8601 Datasheet
Contents
Contents
Revision History ..........................................................................................9
1
2
Introduction.....................................................................................13
Product Overview.............................................................................14
2.1
2.2
2.3
Features ........................................................................................................... 14
Applications....................................................................................................... 15
Block Diagram ................................................................................................... 16
3
Functional Descriptions....................................................................17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Interface and Media............................................................................................ 17
MAC Interface.................................................................................................... 17
3.2.1
MAC Resistor Calibration .......................................................................... 17
3.2.2
RGMII MAC Interface Mode ...................................................................... 17
Cat5 Media Interface .......................................................................................... 18
Cat5 Auto-Negotiation ........................................................................................ 19
Manual MDI/MDI-X Setting .................................................................................. 20
Automatic Crossover and Polarity Detection ........................................................... 20
Link Speed Downshift ......................................................................................... 21
Transformerless Ethernet..................................................................................... 21
Ethernet Inline Powered Devices .......................................................................... 21
ActiPHY Power Management................................................................................. 23
3.10.1 Low-Power State .................................................................................... 24
3.10.2 Link Partner Wake-Up State ..................................................................... 25
3.10.3 Normal Operating State ........................................................................... 25
Serial Management Interface ............................................................................... 25
3.11.1 SMI Frames ........................................................................................... 25
3.11.2 SMI Interrupts ....................................................................................... 27
LED Interface .................................................................................................... 28
3.12.1 Simple or Enhanced LED Method............................................................... 28
3.12.2 LED Modes............................................................................................. 28
3.12.3 LED Behavior ......................................................................................... 30
Testing Features................................................................................................. 30
3.13.1 Ethernet Packet Generator (EPG) .............................................................. 30
3.13.2 CRC Counters......................................................................................... 31
3.13.3 Far-end Loopback ................................................................................... 31
3.13.4 Near-End Loopback ................................................................................. 32
3.13.5 Connector Loopback................................................................................ 32
3.13.6 VeriPHY Cable Diagnostics........................................................................ 33
3.13.7 IEEE 1149.1 JTAG Boundary Scan ............................................................. 33
3.13.8 JTAG Instruction Codes............................................................................ 34
3.13.9 Boundary-Scan Register Cell Order............................................................ 36
3.11
3.12
3.13
4
Configuration ...................................................................................37
4.1
4.2
Registers........................................................................................................... 37
4.1.1
Reserved Registers ................................................................................. 38
4.1.2
Reserved Bits ......................................................................................... 38
IEEE Standard and Main Registers ........................................................................ 38
4.2.1
Mode Control ......................................................................................... 39
4.2.2
Mode Status........................................................................................... 40
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VSC8601 Datasheet
Contents
4.3
4.4
4.5
4.2.3
Device Identification ............................................................................... 41
4.2.4
Auto-Negotiation Advertisement ............................................................... 41
4.2.5
Link Partner Auto-Negotiation Capability .................................................... 42
4.2.6
Auto-Negotiation Expansion ..................................................................... 43
4.2.7
Transmit Auto-Negotiation Next Page......................................................... 43
4.2.8
Auto-Negotiation Link Partner Next Page Receive ........................................ 44
4.2.9
1000BASE-T Control................................................................................ 44
4.2.10 1000BASE-T Status................................................................................. 45
4.2.11 Main Registers Reserved Addresses ........................................................... 45
4.2.12 1000BASE-T Status Extension 1................................................................ 45
4.2.13 100BASE-TX Status Extension .................................................................. 46
4.2.14 1000BASE-T Status Extension 2................................................................ 46
4.2.15 Bypass Control ....................................................................................... 47
4.2.16 Receive Error Counter ............................................................................. 48
4.2.17 False Carrier Sense Counter ..................................................................... 48
4.2.18 Disconnect Counter................................................................................. 49
4.2.19 Extended Control and Status .................................................................... 49
4.2.20 Extended PHY Control Set 1 ..................................................................... 50
4.2.21 Extended PHY Control Set 2 ..................................................................... 50
4.2.22 Interrupt Mask ....................................................................................... 51
4.2.23 Interrupt Status ..................................................................................... 52
4.2.24 LED Control ........................................................................................... 52
4.2.25 Auxiliary Control and Status ..................................................................... 53
4.2.26 Delay Skew Status.................................................................................. 54
4.2.27 Reserved Address Space .......................................................................... 54
Extended Page Registers ..................................................................................... 55
4.3.1
Extended Page Access ............................................................................. 56
4.3.2
Enhanced LED Method Select ................................................................... 56
4.3.3
Enhanced LED Behavior ........................................................................... 57
4.3.4
CRC Good Counter .................................................................................. 58
4.3.5
MAC Resistor Calibration Control ............................................................... 58
4.3.6
Extended PHY Control 3........................................................................... 59
4.3.7
EEPROM Interface Status and Control ........................................................ 59
4.3.8
EEPROM Data Read/Write ........................................................................ 60
4.3.9
Extended PHY Control 4........................................................................... 60
4.3.10 Reserved Extended Registers ................................................................... 61
4.3.11 Extended PHY Control 5........................................................................... 61
4.3.12 RGMII Skew Control................................................................................ 62
4.3.13 Ethernet Packet Generator (EPG) Control 1 ................................................ 63
4.3.14 Ethernet Packet Generator Control 2 ......................................................... 64
CMODE ............................................................................................................. 64
4.4.1
CMODE Pins and Related Functions ........................................................... 64
4.4.2
Functions and Related CMODE Pins ........................................................... 65
4.4.3
CMODE Resistor Values............................................................................ 65
EEPROM............................................................................................................ 66
4.5.1
EEPROM Contents Description .................................................................. 66
4.5.2
Read/Write Access to the EEPROM ............................................................ 67
5
Electrical Specifications ...................................................................69
5.1
5.2
DC Characteristics .............................................................................................. 69
5.1.1
VDDIO at 3.3 V ...................................................................................... 69
5.1.2
VDDIO at 2.5 V ...................................................................................... 70
Current Consumption.......................................................................................... 70
5.2.1
Consumption with 1000BASE-T Link .......................................................... 70
5.2.2
Consumption with 100BASE-TX Link .......................................................... 71
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Contents
5.3
5.4
5.5
5.2.3
Consumption with 10BASE-T Link.............................................................. 72
5.2.4
Consumption with No Link and ActiPHY Enabled .......................................... 73
5.2.5
Consumption with No Link and ActiPHY Disabled ......................................... 73
5.2.6
Consumption in Power-Down Mode............................................................ 74
5.2.7
Consumption in Reset State ..................................................................... 75
AC Characteristics .............................................................................................. 75
5.3.1
Reference Clock Input ............................................................................. 76
5.3.2
Clock Output .......................................................................................... 76
5.3.3
JTAG Interface ....................................................................................... 77
5.3.4
SMI Interface ......................................................................................... 77
5.3.5
Device Reset .......................................................................................... 78
5.3.6
RGMII Uncompensated ............................................................................ 80
5.3.7
RGMII Compensated ............................................................................... 81
Operating Conditions .......................................................................................... 82
Stress Ratings ................................................................................................... 83
6
Pin Descriptions ...............................................................................84
6.1
6.2
Pin Diagram ...................................................................................................... 84
Pins by Function................................................................................................. 85
6.2.1
Twisted Pair Interface .............................................................................. 85
6.2.2
RGMII MAC Interface .............................................................................. 86
6.2.3
Serial Management Interface (SMI)........................................................... 87
6.2.4
JTAG ..................................................................................................... 88
6.2.5
Miscellaneous......................................................................................... 88
6.2.6
Power Supply ......................................................................................... 89
6.2.7
Power Supply and Associated Function....................................................... 90
Pins by Name .................................................................................................... 91
Pins by Number ................................................................................................. 92
6.3
6.4
7
Package Information........................................................................93
7.1
7.2
7.3
Package Drawing................................................................................................ 93
Thermal Specifications ........................................................................................ 95
Moisture Sensitivity ............................................................................................ 95
8
Design Considerations .....................................................................96
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
RX_CLK Can Reach as High as 55% Duty Cycle ...................................................... 96
First SMI Write Fails after Software Reset .............................................................. 96
Link-Up Issue In Forced 100BASE-TX Mode ............................................................ 96
Default 10Base-T Settings Are Marginal and Cause MAU Test Failure.......................... 97
On-Chip Pull-up Resistor Violation......................................................................... 99
Setting the Internal RGMII Timing Compensation Value ........................................... 99
10BASE-T Harmonics at 30 MHz and 50 MHz Marginally Violate Specification .............. 99
Voltage Overshoot When Using On-Chip Switching Regulator.................................. 100
Long Link-Up Times Caused by Noise on the Twisted Pair Interface ......................... 100
High VDD33 and Low VDDIOMAC Supply ............................................................. 101
9
Ordering Information .....................................................................102
Revision 4.1
September 2009
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