Datasheet
Supervisor IC
System Power Good + Watchdog Timer +
Reset for Automotive
BD39040MUF-C
General Description
BD39040MUF-C is a supervisor IC with quad power
good, Watchdog timer and reset. This IC enables existing
system to improve its ASIL level easily.
The BD39040MUF-C includes built-in self-test (BIST).
Key Specifications
VDD Input Voltage Range:
2.7 V to 5.5 V
(VDD voltage level needs to be fixed within this range
in 10% accuracy to avoid RSTIN reset detection)
Detection Voltage (VDD POR/Power Good)
Under Voltage Detection:
-10 % (3 % accuracy)
Over Voltage Detection:
+10 % (3 % accuracy)
Reset Off Time:
10 ms
Operating Temperature Range: -40 °C to +125 °C
Features
AEC-Q100 Qualified
(Note 1)
Quad Power Good for External Inputs
Over Voltage Detection (OVD)
Under Voltage Detection (UVD)
Adjustable Window Watchdog Timer(WDT)
Reset for VDD Input (POR)
Built-in Self-test (BIST)
Special Characteristics
Reference Voltage Accuracy
Under Voltage Detection:
Over Voltage Detection:
±3.0 %
±3.0 %
(Note 1)
Grade 1
Applications
Automotive for ADAS
Camera Module
Microwave Module
Power Train ECU
Other ECU
Package
VQFN16FV3030
W (Typ) x D (Typ) x H (Max)
3.00 mm x 3.00 mm x 1.00 mm
Close-up
Typical Application Circuit
Battery
VO1
VQFN16FV3030
Wettable Flank Package
RSTIN
VO2
VDD
XRSTOUT
DIN1
PG1
VO3
PMIC/
Discrete DCDC
VO4
DIN2
PG2
DIN3
BD39040MUF-C
PG3
Processor
VO5
DIN4
PG4
WDIN
WDEN
RTW
GND
WDOUT
〇Product
structure : Silicon integrated circuit
www.rohm.com
© 2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 14 • 001
〇This
product has no designed protection against radioactive rays
1/26
TSZ02201-0A3A0AM00460-1-2
15.Feb.2019 Rev.001
BD39040MUF-C
Contents
General Description ................................................................................................................................................................ 1
Features ................................................................................................................................................................................. 1
Applications ............................................................................................................................................................................ 1
Key Specifications................................................................................................................................................................... 1
Special Characteristics ............................................................................................................................................................ 1
Package
............................................................................................................................................................................. 1
Typical Application Circuit ........................................................................................................................................................ 1
Pin Configuration .................................................................................................................................................................... 3
Pin Descriptions ...................................................................................................................................................................... 3
Block Diagram ........................................................................................................................................................................ 4
Absolute Maximum Ratings ..................................................................................................................................................... 9
Thermal Resistance ................................................................................................................................................................ 9
Recommended Operating Conditions ...................................................................................................................................... 9
Electrical Characteristics ..................................................................................................................................................... 10
Typical Performance Curves .................................................................................................................................................. 12
Timing Chart ......................................................................................................................................................................... 16
Application Example.............................................................................................................................................................. 20
Operational Notes ................................................................................................................................................................. 22
Ordering Information ............................................................................................................................................................. 24
Marking Diagram................................................................................................................................................................... 24
Physical Dimension and Packing Information ......................................................................................................................... 25
Revision History .................................................................................................................................................................... 26
www.rohm.com
© 2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
2/26
TSZ02201-0A3A0AM00460-1-2
15.Feb.2019 Rev.001
BD39040MUF-C
Pin Configuration
(TOP View)
DIN4
DIN3
PG4
PG3
12
WDEN
13
11
10
9
8
PG2
WDIN
14
EXP-PAD
7
DIN2
XRSTOUT
15
6
PG1
WDOUT
16
1
VDD
5
2
RSTIN
DIN1
3
GND
4
RTW
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
VDD
RSTIN
GND
RTW
DIN1
PG1
DIN2
PG2
DIN3
PG3
DIN4
PG4
WDEN
WDIN
Function
IC’s Power Source
The VDD pin voltage divided by external resistor input pin. Nominal voltage level
needs to be 0.8 V.
IC’s Power Ground
WDT frequency setting pin. FAST Timeout and SLOW Timeout is adjusted by
the resistor value for this pin.
Voltage for monitoring channel divided by external resistor input pin. Nominal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN1 pin, and Nch Open Drain output.
Hi-Z for assertion, and Low for de-assertion is its value. Please be pulled-up by
external resistor.
It can be pulled-up to any voltage source.
Voltage for monitoring channel divided by external resistor input pin. Nominal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN2 pin, and Nch Open Drain output.
Hi-Z for assertion, and Low for de-assertion is its value. Please be pulled-up by
external resistor.
It can be pulled-up to any voltage source.
Voltage for monitoring channel divided by external resistor input pin. Nominal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN3 pin, and Nch Open Drain output.
Hi-Z for assertion, and Low for de-assertion is its value. Please be pulled-up by
external resistor.
It can be pulled-up to any voltage source.
Voltage for monitoring channel divided by external resistor input pin. Nominal
voltage level needs to be 0.8 V.
POWER GOOD output pin for the DIN4 pin, and Nch Open Drain output.
Hi-Z for assertion, and Low for de-assertion is its value. Please be pulled-up by
external resistor.
It can be pulled-up to any voltage source.
Enable pin for WDT. High=Active, Low=Disable and WDT error is ignored.
Clock input pin for WDT
Reset output pin. Nch Open Drain output.
Hi-Z for normal, and Low for abnormal (reset) is its value. Please be pulled-up
by external resistor.
It can be pulled-up to any voltage source. Either error of OVD, UVD for RSTIN,
reference voltage monitoring, internal OSC monitoring, WDT and BIST at
power-up sequence causes this pin to drive low.
Buffer output pin for the WDEN pin input. Abnormal Power Source / the GND pin
shortage for the WDEN pin can be recognized by monitoring this pin. This pin
becomes Low when the XRSTOUT pin is low.
The EXP-PAD is connected to the PCB Ground plane.
15
XRSTOUT
16
-
WDOUT
EXP-PAD
www.rohm.com
© 2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
3/26
TSZ02201-0A3A0AM00460-1-2
15.Feb.2019 Rev.001
BD39040MUF-C
Block Diagram
VDD
VREF
VREF_DET
VREF_DET
VREF_SUB
BIST_EN
UVLO
UVLO
RSTIN
VREF_DET
RSTIN_DET
BIST_ERROR
WDT_DET
CLK_DET
WDT_OSC_DET
XRSTOUT
XRSTOUT_DET
OVD
+
-
BIST_EN
OVD_RST
RSTIN_DET
Filter
UVD_RST
Counter
UVD
+
BIST_EN
DIN1
VREF
DIN2
VREF
DIN3
VREF
DIN4
VREF
BIST_EN
RTW
WDIN
XRSTOUT_DET
WDEN
UVLO
www.rohm.com
© 2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
+
+
+
+
-
-
-
-
-
VREF_DET
OVD_RST
UVD_RST
OVD1,OVD2,
OVD3,OVD4
OVD1
UVD1,UVD2,
UVD3,UVD4
BIST
BIST_ERROR
OVD2
OVD
+
-
BIST_EN
UVD
UVD1
BIST_EN
VREF_DET
Filter
Counter
PG1
BIST_EN
OVD
+
-
OVD2
VREF_DET
PG2
BIST_EN
UVD
UVD2
Filter
Counter
DIGITAL
BIST_EN
OVD
+
OVD3
VREF_DET
-
BIST_EN
UVD
UVD3
Filter
PG3
Counter
BIST_EN
OVD
+
-
BIST_EN
UVD
UVD4
Filter
OVD4
VREF_DET
Counter
PG4
DIGITAL_OSC
CLK_DET
CLK_DET
WDT_OSC
WDT_OSC_DET
WDT_DET
WDT
VDD
WDOUT
Counter
4/26
TSZ02201-0A3A0AM00460-1-2
15.Feb.2019 Rev.001
BD39040MUF-C
Block Diagrams - continued
Description of Blocks
Reference Voltage (VREF)
VREF is used for the reference voltage of monitoring each input voltage.
Reference Voltage (VREF_SUB)
VREF_SUB is used for the reference voltage of mutual monitoring VREF.
Reference Voltage (VREF_DET)
This is monitoring the 2 reference voltage, VREF and VREF_SUB.
This block contributes to the higher reliability by continuous, mutual monitoring each other if it turns on correctly.
Occurrence of error leads to Low output at the XRSTOUT pin and which is never de-asserted as long as abnormal status
lasts. It becomes High at 10 ms (Typ) after the voltage returned to the normal range.
Under Voltage Lockout Circuit (UVLO)
Protection circuit to prevent internal circuit from malfunction at lower voltage (Power-up sequence or input power supply
drop). This is monitoring the VDD pin voltage and UVLO works when it goes down to threshold level.
As UVLO is detected, the XRSTOUT, WDOUT, PG1, PG2, PG3 and PG4 pins output Low. Also Counter value in DIGITAL
BLOCK is initialized and DIGITAL_OSC/WDT_OSC stop working.
Oscillator (DIGITAL_OSC)
This OSC generates the clock to control DIGITAL BLOCK. The frequency of DIGITAL_OSC is fixed at 2.2 MHz
Oscillator (WDT_OSC)
This OSC generates the clock to control WDT.
The frequency of WDT_OSC is possible to be adjusted by the resistor value, so that FAST Timeout / SLOW Timeout is
changed by that.
WDT_OSC has the function to stop its working when the external resistor at the RTW pin is shorted or OPEN
(WDT_OSC_DET). Once CLK_DET is detected, XRSTOUT becomes Low.
Oscillator (CLK_DET)
This block monitors both DIGITAL_OSC and WDT_OSC.
2 OSCs always monitor their frequency each other and it leads to the higher reliability.
When an error happened at the monitoring, XRSTOUT becomes Low.
Over Voltage Detection (OVD1, OVD2, OVD3, OVD4, OVD_RST)
When input voltage goes over the threshold level, OVD is detected and the PG1, PG2, PG3 and PG4 pins are driven by Low.
Detecting pins are DIN1, DIN2, DIN3 and DIN4 and RSTIN. OVD detection for the DIN1, DIN2, DIN3 and DIN4 pins causes
corresponding the PG1, PG2, PG3 and PG4 pins to become Low. OVD detection for RSTIN causes the XRSTOUT pin to
become Low. These output signals become High at 10 ms (Typ) after each input pin returns within the nominal voltage range.
And each input has a filter in DIGITAL BLOCK, then overshoot within 50 µs (Min) is ignored.
Under Voltage Detection (UVD1, UVD2, UVD3, UVD4, UVD_RST)
When input voltage goes below the threshold level, UVD is detected and the PG1, PG2, PG3 and PG4 pins are driven by Low.
Detecting pins are DIN1, DIN2, DIN3, DIN4 and RSTIN. UVD detection for the DIN1, DIN2, DIN3 and DIN4 pins causes
corresponding the PG1, PG2, PG3 and PG4 pins to become Low. UVD detection for RSTIN causes the XRSTOUT pin to
become Low. These output signals become High at 10 ms (Typ) after each input pin returns within the nominal voltage range.
And each input has a filter in DIGITAL BLOCK, then undershoot within 50 µs (Min) is ignored.
BIST
When VDD Power on Reset (monitoring the RSTIN pin) is released, BIST is performed and self-test for DIN1, DIN2, DIN3,
DIN4, RSTIN and VREF_DET comparators are executed to see if each comparator correctly toggles their High/Low output
based on input level change.
BIST time (t
BIST
) is 2 ms (Max). Once BIST ends without any errors, XRSTOUT becomes High. If an error is found during BIST,
XRSTOUT keeps Low and BIST is repeated until it passes.
Watchdog Timer (WDT)
Watchdog Timer (WDT) monitors microprocessor’s operation by detecting the time from both rise and fall edge of WDIN. If
BIST result is abnormality, WDT does not work and XRSTOUT is kept low. WDT is activated when WDOUT=High, and both
WDEN and XRSTOUT have to be High in order to get WDOUT to be High.
As long as the duty of WDIN clock is kept within “Trigger open window” in Figure 1, WDT does not detect any errors and
XRSTOUT stays at High.
www.rohm.com
© 2017 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
5/26
TSZ02201-0A3A0AM00460-1-2
15.Feb.2019 Rev.001
淘e淘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
