Datasheet
3.5 V to 40 V Input, 2 A
Single 2.2 MHz Buck DC/DC Converter
For Automotive
BD9P2x5EFV-C Series
General Description
BD9P2x5EFV-C Series are current mode synchronous
buck DC/DC converter integrating POWER MOSFETs.
Key Specifications
Input Voltage Range:
3.5 V to 40 V
(Initial startup is 4.0 V or more)
Output Voltage Range
BD9P205EFV-C:
0.8 V to 8.5 V
BD9P235EFV-C:
3.3 V (Typ)
BD9P255EFV-C:
5.0 V (Typ)
Output Current:
OCP_SEL = H
1.5 A (Max)
OCP_SEL = L
2.0 A (Max)
2.2 MHz (Typ)
Switching Frequency:
Output Voltage Accuracy:
±1.75 % (-40 °C to +125 °C)
Shutdown Current:
2.1 μA (Typ)
Operating Temperature Range: -40 °C to +125 °C
Features
Nano Pulse Control
(Note 1)
AEC-Q100 Qualified
Minimum ON Pulse 50 ns (Max)
Synchronous Buck DC/DC Converter Integrating
POWER MOSFETs
Soft Start Function
Current Mode Control
Reset Function
Quiescent Current 10 μA (Typ)
with 12 V Input to 5.0 V Output
Light Load Mode (LLM)
Forced Pulse Wide Modulation (PWM) Mode
Phase Compensation Included
Selectable Spread Spectrum Switching
External Synchronization Function
Selectable Over Current Protection (OCP)
Input Under Voltage Lockout (UVLO) Protection
Thermal Shut Down (TSD) Protection
Output Over Voltage Protection (OVP)
Short Circuit Protection (SCP)
TM
Package
HTSSOP-B20
W (Typ) x D (Typ) x H (Max)
6.5 mm x 6.4 mm x 1.0 mm
(Note 1)
Grade 1
Applications
Automotive Powered Supplies
Consumer Powered Supplies
HTSSOP-B20
Typical Application Circuit
C
BST
VIN
PVIN
V
IN
BST
SW
VCC_EX
VOUT_DIS
L
1
V
OUT
C
IN
EN
PGND
VREG
VOUT_SNS
RESET
MODE
GND
SSCG
R
RST
V
MODE
V
SSCG
C
OUT
C
REG
OCP_SEL
Figure 1. Application Circuit with Discharge Function (BD9P235EFV-C, BD9P255EFV-C)
TM
Nano Pulse Control
is a trademark of ROHM Co., Ltd.
〇Product
structure : Silicon integrated circuit
.
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© 2019 ROHM Co., Ltd. All rights reserved.
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BD9P2x5EFV-C Series
Pin Description
Pin No.
1
Pin Name
EN
Function
Enable pin. Apply low level (0.8 V or lower) to disable device and apply high
level (2.0 V or higher) to enable device. This pin must not be left open.
If this pin is connected to other devices, it is recommended to insert a current
limiting resistor to avoid damages caused by a short between pins.
Power supply input pins for the internal circuit.
Connect this pin to the PVIN pins.
Power supply input pins that are used for the output stage of the switching
regulator. Connect input ceramic capacitors referring Page 33 between the
PGND pins and these pins.
This pin is not connected to the chip. Use this as open. If this pin is used other
than open and adjacent pins are expected to be shorted, please confirm if there
is any problem with the actual application.
Ground pins for the output stage of the switching regulator.
Switching node pins. These pins are connected to the source of the internal
High Side FET and the drain of the internal Low Side FET. Connect the power
inductor and the bootstrap capacitor.
Connect a bootstrap capacitor of 0.1 µF (Typ) between this pin and the SW
pins. The voltage of this capacitor is the gate drive of the High Side FET.
This is OCP threshold selective pin. OCP threshold is set to 2.250 A (Typ) at
high, and 3.000 A (Typ) at low. These values mean the average inductor
current. Connect this pin to VREG (High) or GND (Low).
Pin to select FPWM (Forced PWM) mode, AUTO (Automatically switched
between PWM mode and LLM) mode, or SYNC (Activate synchronization)
mode. In case of using FPWM mode, set high. In case of using AUTO mode,
set low or open. In case of using SYNC mode, apply a clock to this pin.
Pin to select Spread Spectrum function. Set high to enable Spread Spectrum
and set low to disable Spread Spectrum. Connect this pin to VREG (High) or
GND (Low).
Output reset pin with open drain. Connect a pull-up resistor to the VREG pin or
the power supply within the absolute maximum voltage ratings of the RESET
pin. Using a 5 kΩ to 100 kΩ resistance is recommended.
Ground pin.
This pin discharges the VOUT node. Connect this pin to the VOUT when
discharge function is required. Otherwise, connect this pin to GND.
Pin to define the clamp voltage of GmAmp2 output and phase compensation.
Connect this pin to the output voltage.
Inverting input node of the GmAmp1. This pin is used for OVP, SCP and
RESET detection. And, this pin is used for defining the clamp voltage of
GmAmp2 output and phase compensation. Connect this pin to the output
voltage.
Inverting input node of the GmAmp1. This pin is used for OVP, SCP and
RESET detection. Connect output voltage divider to this pin to set the output
voltage.
This pin is not connected to the chip. Use this as open. If this pin is used other
than open and adjacent pins are expected to be shorted, please confirm if there
is any problem with the actual application.
This pin is power supply input for internal circuit. VREG voltage is supplied from
VCC_EX when voltage between 3.2 V (V
TEXH
, Max) and 5.65 V (V
EXOVPL
, Min) is
connected to this pin. Connecting this pin to VOUT improves efficiency. In case
of not use this function, connect this pin to GND.
Pin to output 3.3 V (Typ) for internal circuit. Connect a ceramic capacitor of 1.0
µF (Typ). Do not connect to any external loads except the OCP_SEL pin, the
MODE pin, the SSCG pin and a pull-up resistor to the RESET pin.
Exposed pad. The EXP-PAD is connected to the P substrate of the IC. Connect
this pad to the internal PCB ground plane using multiple via holes to obtain
excellent heat dissipation characteristics.
2
3, 4
VIN
PVIN
5
6, 7
8, 9
10
11
N.C.
PGND
SW
BST
OCP_SEL
12
MODE
13
SSCG
14
15
16
17
(BD9P205EFV-C)
17
(BD9P235EFV-C,
BD9P255EFV-C)
18
(BD9P205EFV-C)
18
(BD9P235EFV-C,
BD9P255EFV-C)
19
RESET
GND
VOUT_DIS
VOUT_SNS
FB
N.C.
VCC_EX
20
VREG
-
EXP-PAD
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