V-Data
Revision History
Revision 1 ( Dec. 2001 )
1.Fister release.
VDD8616A8A
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3.
Changed AC Characteristics.
4.
Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002
1
V-Data
Double Data Rate SDRAM
General Description
The VDD8616A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
4,194,304 words x 16 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
VDD8616A8A
4M x 16 Bit x 4 Banks
Features
•2.5V
for VDDQ power supply
•SSTL_2
interface
•MRS
Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
•4
banks operation
•Differential
clock input (CK, /CK) operation
•Double
data rate interface
•Auto
& Self refresh
•8192
refresh cycle
•DQM
for masking
•Package:66-pins
400 mil TSOP-Type II
Ordering Information.
Part No.
VDD8608A8A-75BA
VDD8616A8A-75B
Frequency
133Mhz(7.5ns /CL=2)
133Mhz(7.5ns /CL=2.5)
Interface
SSTL_2
Package
400mil 66pin TSOPII
Pin Assignment
V
D D
D Q0
V
DD Q
NC
DQ1
V
SSQ
NC
DQ2
V
DD Q
NC
DQ3
V
SSQ
NC
NC
V
DQ
D
NC
NC
V
D D
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
6
6
65
6
4
6
3
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
S S
DQ7
V
S SQ
NC
DQ6
V
DDQ
NC
DQ5
V
S SQ
NC
DQ4
V
DD Q
NC
NC
V
S S Q
DQS
NC
V
R E F
V
S S
DM
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
S S
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
V-Data
Pin Description
PIN
CK, /CK
CKE
NAME
System Clock
Clock Enable
Differential clock input.
FUNCTION
VDD8616A8A
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
A0~A12
Chip Select
Address
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
BS0~BS1
Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS
low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
Reference voltage for inputs for SSTL interface.
This pin is recommended to be left No Connection on the device.
DQ0~DQ15 Data
/RAS
/CAS
/WE
VDD/VSS
VREF
NC
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply/Ground
Reference Voltage
No Connection
V
DDQ
/V
SSQ
Data Output Power/Ground
Block Diagram
CK
CKE
Address
Clock
Generator
Bank3
Bank2
Bank1
Row Decoder
Mode
Register
Address
Buffer
&
Refresh
Counter
Bank0
Amplifier
Command Decoder
/RAS
/CAS
/WE
Control Logic
/CS
Data Latch
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
DQM
DQS
Data Control Circuit
DQ0~DQn
Rev 2 April, 2002
3
V-Data
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
out
V
DD
, V
DDQ
T
STG
P
D
I
OUT
Value
-0.3 ~ VDDQ+0.3
-0.3 ~ 3.6
-55 ~ +150
1
50
VDD8616A8A
Unit
V
V
℃
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
℃
Parameter
Supply voltage
Supply voltage
Input logic high voltage
Input logic low voltage
Differential Clock DC Input voltage
Input Differential CLK&/CLK voltage
Input leakage current
Output leakage current
Reference Voltage
Termination Voltage
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
ICK
V
ID
I
IL
I
OL
V
REF
V
TT
Min
2.3
2.3
V
REF
+0.15
-0.3
-0.3
0.7
-5
-5
0.49* V
DDQ
V
REF
-0.04
Max
2.7
V
DD
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
5
5
0.51* V
DDQ
V
REF
+0.04
V
V
V
V
uA
uA
V
V
5
3
4
2
Unit
V
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DDQ
.
2.V
IL
(min)=-0.9V with a pulse width
≦
5ns .
3.Any input 0V
≦
V
IN
≦
3.6V, all other pins are not under test = 0V.
4.Dout is disabled, 0V
≦
V
OUT
≦
2.7V.
5. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of
the same. Peak to peak noise on V
REF
may not exceed
±2%
of the DC value.
Rev 2 April, 2002
4
V-Data
AC Test Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
℃
Parameter
AC input high level voltage
AC input low level voltage
Input Reference Voltage
Termination Voltage
Input Signal Peak to Peak Swing
Input Difference Voltage. CLK and /CLK Inputs
Symbol
V
IH
V
IL
VREF
VTT
V
SWING
V
ID
Value
VREF+0.31
VREF-0.31
0.5xV
DDQ
0.5xV
DDQ
1.0
1.5
VDD8616A8A
Unit
V
V
V
V
V
V
Note
Capacitance
TA=25℃, f-=1Mhz
Parameter
Input capacitance
CK, /CK
A0~A12,BS0,BS1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Data input / output capacitance DQM
CI/O
4
5
pF
Pin
Symbol
Cl1
Cl2
Min
2
2
Max
3.0
3.0
Unit
pF
pF
Output load circuit
V
tt
=0.5*V
DDQ
R
T
=50Ω
Output
Z0=50Ω
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
Output Load Circuit (SSTL_2)
Rev 2 April, 2002
5
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