MRT
Two Terminal Side interfaces are provided, a positive and negative rail (RP and RN) or NRZ (RD) interface.
The selection is determined by the state placed on the signal lead labeled PNENB. When a low is applied to
the signal lead, the HDB3 Decoder and HDB3 Encoder Blocks are bypassed, and the terminal side I/O is a
positive and negative rail interface. When a high is applied to the signal lead, an NRZ interface is provided.
Data is clocked out of the MRT on negative edges of the clock signal (CLKO). Receive data and the clock sig-
nals are disabled, and forced to a high impedance state by placing a low on the receive disable lead (RXDIS).
For a receive positive and negative rail interface, an inverted clock (CLKO) is also provided.
The terminal side interface for the transmitter can either be positive and negative rail (TP and TN) or NRZ (TD)
data depending on the state of the common control lead PNENB. Data is clocked into the MRT on positive
transitions of the clock signal (CLKI). The input clock is monitored for the loss of clock. When the input clock
remains high or low, TXLOC will be set low. The MRT also provides the capability to generate and insert AIS
(all ones signal), independent of the transmit data. A low placed on the TXAIS lead enables the transmit AIS
generator.
Two loopbacks are provided, transmit loopback and receive loopback. Transmit loopback connects the data
path from the transmitter output driver stage to the clock recovery, and disables the external receiver input.
Transmit loopback is activated by placing a low on the LBKTX signal lead.
Receive loopback connects the receive data path to the transmit output circuits and disables the transmit input.
Receive loopback is activated by placing a low on the LBKRX signal lead.
For 6 Mbps operation, the MRT should be operated in the P and N rail mode, bypassing the HDB3 Decoder/
Encoder.
PIN DIAGRAM
BERCK
LQLTY
TXLOC
RXAIS
TXAIS
TP/TD
40
38
36
34
32
30
20
22
24
26
28
EQB1
EQB0
GND
CLKI
VDD
10
GND
VDD
12
TPO
TNO
GND
GNDA
16
18
DI2
DI1
GND
GND
GND
VDD
LOW
42
LBKTX
TN
6
4
2
VCOC
PNENB
DCK
VDD
GND
RN
RP/RD
CLKO
CLKO
GND
PLLC
14
8
MRT PIN DIAGRAM
(Top View)
AGFIL
RXLOS
Figure 2. MRT Pin Diagram With Names and Numbers
LBKRX
VDD
RXDIS
CV
VAGC
44
-3-
TXC-02050-MB
Ed. 3, April 1994
MRT
PIN DESCRIPTIONS
Power Supply and Ground
Symbol
VDD
GND
VAGC
GNDA
Pin No.
10,18,35,
37,42
1,6,11,16,32,
36,39,44
23
31
I/O/P*
P
P
P
P
Type
Name/Function
VDD:
5-volt supply,
±
5%.
Ground:
0 volts reference.
AGC VDD:
Isolate from VDD using 1N914 or 1N4148
diode.
AGC Ground:
0 volts reference.
*Note: I = Input; O = Output; P = Power
Line Side I/O
Symbol
DI1
DI2
Pin No.
29
30
I/O/P
I
O
Type
Analog
Analog
Name/Function
Data In 1:
HDB3 or B8ZS encoded bipolar receive
data input.
Data In 2:
DC Voltage Reference for Data Input DI1.
The MRT uses an internally generated voltage refer-
ence as an AC ground for the received data input. An
external 0.1
µ
F capacitor, in parallel with a 10
µ
F/6.3 V
tantalum capacitor, is connected between this pin and
ground. No other connection should be made to this
pin.
Transmit Negative Out:
Line transmit negative; out-
put is an active low.
Transmit Positive Out:
Line transmit positive; output
is an active low.
TNO
TPO
33
34
O
O
TTL24mA
TTL24mA
Terminal Side I/O
Symbol
RN
Pin No.
12
I/O/P
O
Type
TTL4mA
Name/Function
Receive Negative:
When PNENB is low, the HDB3
codec is bypassed and N-rail (RN) data is provided on
this pin. When PNENB is high, the output is forced to
a high impedance state.
Receive Positive/Receive Data:
When PNENB is
low, the HDB3 codec is bypassed and P-Rail (RP)
data is provided on this pin. When PNENB is high,
NRZ data (RD) is provided.
Clock Out Inverted:
Receive inverted clock output.
Positive and negative rail receive data is clocked out
on the rising edge. Disabled in the NRZ mode.
RP/RD
13
O
TTL4mA
CLKO
14
O
CMOS8mA
-4-
TXC-02050-MB
Ed. 3, April 1994
MRT
Symbol
CLKO
Pin No.
15
I/O/P
O
Type
CMOS8mA
Name/Function
Clock Out:
Receive clock output. Receive positive
and negative rail and NRZ data is clocked out on the
falling edge.
Clock In:
Transmit clock input for P and N rail and
NRZ data. Transmit data is clocked into the MRT on
the rising edge. This clock must have a frequency of
±
20 ppm for the 34368 kbit/s operation and
±
30 ppm
for the 6312/8448 kbit/s operation (ref: CCITT recom-
mendation G.703). The duty cycle requirement for this
clock signal is 50%
±
5%, measured at the 1.4V TTL
threshold level.
Transmit Positive/Transmit Data:
When PNENB is
low, the HDB3 codec is bypassed and transmit P-rail
(TP) data is applied to this pin. When PNENB is high,
NRZ transmit data (TD) is applied.
Transmit Negative:
When PNENB is low, the HDB3
codec is bypassed and transmit N-Rail (TN) is applied
to this pin. When PNENB is high, this input is disabled.
CLKI
38
I
TTLr
TP/TD
40
I
TTL
TN
41
I
TTL
Alarm Signal Outputs
Symbol
TXLOC
Pin No.
2
I/O/P
O
Type
TTL2mA
Name/Function
Transmit Loss Of Clock:
Active low output. A trans-
mit loss of clock alarm occurs when the transmit clock
input (CKLI) is stuck high or low for 20-32 clock cycles.
Recovery occurs on the first input clock transition.
Line Quality:
This signal represents a gross estimate
of the line quality which is determined by counting
coding violations for 34 (8) Mbit/s operation. If the line
error rate exceeds a 10
-6
threshold during a 10 (40)
second interval, LQLTY goes active high. LQLTY is
active low when coding violations do not exceed the
10
-6
threshold in a 10 (40) second interval. The output
on this pin is only valid when the appropriate clock sig-
nal is applied to BERCK. It should be disregarded in
the P and N mode of operation.
Coding Violation:
Active high output. A coding viola-
tion pulse occurs when an HDB3 coding violation is
detected in the received line data input. A coding vio-
lation is not part of the HDB3 zero-substitution code. A
coding violation occurs because of noise or other
impairments affecting the line signal. The output of this
pin should be disregarded in the P and N mode.
Receive Loss Of Signal:
Active low output. A receive
loss of signal occurs when the input data is zero for
20-32 clock cycles. Recovery occurs when the receive
signal returns.
LQLTY
5
O
TTL2mA
CV
19
O
TTL2mA
RXLOS
20
O
TTL2mA
-5-
TXC-02050-MB
Ed. 3, April 1994
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