a

FEATURES

Four Independent Sample-and-Holds

Internal Hold Capacitors

High Accuracy: 12 Bit

Very Low Droop Rate: 2 mV/s typ

Output Buffers Stable for C

L

≤

500 pF

TTL/CMOS Compatible Logic Inputs

Single or Dual Supply Applications

Monolithic Low Power CMOS Design

APPLICATIONS

Signal Processing Systems

Multichannel Data Acquisition Systems

Automatic Test Equipment

Medical and Analytical Instrumentation

Event Analysis

DAC Deglitching

CMOS Quad

Sample-and-Hold Amplifier

SMP04*

FUNCTIONAL BLOCK DIAGRAM

V

DD

SMP04

V

IN1

S/H

1

V

SS

V

IN2

S/H

2

V

SS

V

IN3

S/H

3

V

SS

V

IN4

S/H

4

V

SS

V

OUT4

V

OUT3

V

OUT2

V

OUT1

V

SS

DGND

GENERAL DESCRIPTION

The SMP04 is a monolithic quad sample-and-hold; it has four

internal precision buffer amplifiers and internal hold capacitors.

It is manufactured in ADI’s advanced oxide isolated CMOS

technology to obtain the high accuracy, low droop rate and fast

acquisition time required by data acquisition and signal process-

ing systems. The device can acquire an 8-bit input signal to

±

1/2 LSB in less than four microseconds. The SMP04 can

operate from single or dual power supplies with TTL/CMOS

logic compatibility. Its output swing includes the negative supply.

The SMP04 is ideally suited for a wide variety of sample-and-

hold applications, including amplifier offset or VCA gain adjust-

ments. One or more can be used with single or multiple DACs

to provide multiple setpoints within a system.

The SMP04 offers significant cost and size reduction over

equivalent module or discrete designs. It is available in a

16-lead hermetic or plastic DIP and surface mount SOIC

packages. It is specified over the extended industrial tem-

perature range of –40°C to +85°C.

*Protected

by U.S. Patent No. 4,739,281.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

SMP04–SPECIFICATIONS

(@ V

DD

= +12.0 V, V

SS

= DGND = 0 V, R

L

= No Load, T

A

= Operating Temperature Range

specified in Absolute Maximum Ratings, unless otherwise noted.)

Parameter

Linearity Error

Buffer Offset Voltage

Hold Step

Droop Rate

Output Source Current

1

Output Sink Current

1

Output Voltage Range

LOGIC CHARACTERISTICS

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

DYNAMIC PERFORMANCE

Acquisition Time

3

Acquisition Time

3

Hold Mode Settling Time

Slew Rate

4

Capacitive Load Stability

Analog Crosstalk

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio

Supply Current

Power Dissipation

2

ELECTRICAL CHARACTERISTICS

Symbol

V

OS

V

HS

∆V/∆t

I

SOURCE

I

SINK

OVR

Conditions

V

IN

= 6 V

V

IN

= 6 V, T

A

= +25°C to +85°C

V

IN

= 6 V, T

A

= –40°C

V

IN

= 6 V, T

A

= +25°C

V

IN

= 6 V

V

IN

= 6 V

R

L

= 20 kΩ

R

L

= 10 kΩ

Min

–10

Typ

0.01

±

2.5

2

Max

+10

4

5

25

10.0

9.5

Units

%

mV

mV/s

mA

V

µA

µs

V/µs

pF

dB

mA

mW

1.2

0.5

0.06

2.4

0.5

V

INH

V

INL

I

IN

t

AQ

t

AQ

t

H

SR

C

L

T

A

= +25°C, 0 V to 10 V Step to 0.1%

–40°C

≤

T

A

≤

+85°C

T

A

= +25°C, 0 V to 10 V Step to 0.01%

To 1 mV

R

L

= 20 kΩ

<30% Overshoot

0 V to 10 V Step

10.8 V

≤

V

DD

≤

13.2 V

0.8

1

4.25

5.25

3

3.5

3.75

9

1

4

500

–80

75

4

PSRR

I

DD

P

DIS

60

7

84

= +5.0 V, V

SS

= –5.0 V, DGND = 0.0 V, R

L

= No Load, T

A

= Operating Temperature

Range specified in Absolute Maximum Ratings, unless otherwise noted.)

DD

ELECTRICAL CHARACTERISTICS

(@ V

Parameter

Symbol

V

OS

V

HS

∆V/∆t

R

OUT

I

SOURCE

I

SINK

OVR

V

INH

V

INL

I

IN

t

AQ

t

AQ

t

H

SR

C

L

PSRR

I

DD

P

DIS

Conditions

V

IN

= 0 V

V

IN

= 0 V, T

A

= +25°C to +85°C

V

IN

= 0 V, T

A

= –40°C

V

IN

= 0 V, T

A

= +25°C

V

IN

= 0 V

V

IN

= 0 V

R

L

= 20 kΩ

Min

–10

Typ

0.01

±

2.5

2

1

Max

+10

4

5

25

Units

%

mV

mV/s

Ω

mA

V

µA

µs

V/µs

pF

dB

mA

mW

Linearity Error

Buffer Offset Voltage

Hold Step

Droop Rate

Output Resistance

Output Source Current

1

Output Sink Current

1

Output Voltage Range

LOGIC CHARACTERISTICS

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

DYNAMIC PERFORMANCE

Acquisition Time

3

Acquisition Time

3

Hold Mode Settling Time

Slew Rate

5

Capacitive Load Stability

2

1.2

0.5

–3.0

2.4

0.5

+3.0

0.8

1

11

–3 V to +3 V Step to 0.1%

–3 V to +3 V Step to 0.01%

To 1 mV

R

L

= 20 kΩ

<30% Overshoot

±

5 V

≤

V

DD

≤ ±

6 V

3.6

9

1

3

500

60

75

3.5

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio

Supply Current

Power Dissipation

5.5

55

NOTES

1

Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels.

2

All input control signals are specified with t

R

= t

F

= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

3

This parameter is guaranteed without test.

4

Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%.

5

Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%.

Specifications are subject to change without notice.

–2–

REV. D

SMP04

ABSOLUTE MAXIMUM RATINGS

(T

A

= +25°C unless otherwise noted)

Package Type

16-Lead Cerdip

16-Lead Plastic DIP

16-Lead SO

*

JA

*

JC

Units

°C/W

V

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V

V

DD

to V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V, 17 V

V

LOGIC

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

DD

V

IN

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

SS

, V

DD

V

OUT

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

SS

, V

DD

Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .

±

20 mA

(Not Short-Circuit Protected)

Digital Input Voltage to DGND . . . . . . . –0.3 V, V

DD

+ 0.3 V

Operating Temperature Range

EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

94

76

92

12

33

27

is specified for worst case mounting conditions, i.e.,

JA

is specified for device

in socket for cerdip and plastic DIP packages;

JA

is specified for device soldered

to printed circuit board for SO package.

CAUTION

1. Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; function operation

at or above this specification is not implied. Exposure to the above maximum

rating conditions for extended periods may affect device reliability.

2. Digital inputs and outputs are protected; however, permanent damage may

occur on unprotected units from high energy electrostatic fields. Keep units in

conductive foam or packaging at all times until ready to use. Use proper antistatic

handling procedures.

3. Remove power before inserting or removing units from their sockets.

PIN CONNECTIONS

16-Lead Cerdip

16-Lead Plastic DIP

16-Lead SO

V

OUT2

1

V

OUT1

2

V

IN1

3

NC 4

16 V

DD

15 V

OUT3

14 V

OUT4

ORDERING GUIDE

Model

SMP04EQ

SMP04EP

SMP04ES

Temperature

Range

–40°C to +85°C

Package

Description

Cerdip-16

PDIP-16

SO-16

Package

Options*

Q-16

N-16

R-16A

13 V

SS

TOP VIEW

V

IN2

5 (Not to Scale) 12 V

IN4

S/H

1

6

S/H

2

7

DGND 8

11 V

IN3

10

S/H

4

9

S/H

3

SMP04

*Q = Cerdip; N = Plastic DIP; R = Small Outline.

NC = NO CONNECT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the SMP04 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. D

–3–

SMP04

V

OUT1

V

OUT2

V

DD

V

OUT3

V

OUT4

V

IN1

V

IN2

V

SS

V

IN4

V

IN3

S/H

1

S/H

2

DGND

S/H

3

S/H

4

Dice Characteristics

Die Size: 0.80 x 0.120 mil = 9,600 sq. mil

(2.032 x 3.048mm = 6.193 sq. mm)

WAFER TEST LIMITS

Parameter

Buffer Offset Voltage

Hold Step

Droop Rate

Output Source Current

Output Sink Current

Output Voltage Range

(@ V

DD

= +12 V, V

SS

= DGND = 0 V, R

L

= No Load, T

A

= +25 C, unless otherwise noted.)

Symbol

V

OS

V

HS

∆V/∆t

I

SOURCE

I

SINK

OVR

Conditions

V

IN

= +6 V

V

IN

= +6 V

V

IN

= +6 V

V

IN

= +6 V

V

IN

= +6 V

R

L

= 20 kΩ

R

L

= 10 kΩ

SMP04G

Limits

±

10

±

4

25

1.2

0.5

0.06/10.0

0.06/9.5

2.4

0.8

1

10.8 V

≤

V

DD

≤

13.2 V

60

7

84

Units

mV max

mV/s max

mA min

V min/max

V min

V max

µA

max

dB min

mA max

mW max

LOGIC CHARACTERISTICS

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

SUPPLY CHARACTERISTICS

Power Supply Rejection Ratio

Supply Current

Power Dissipation

V

INH

V

INL

I

IN

PSRR

I

DD

P

DIS

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

–4–

REV. D

Typical Performance Characteristics–SMP04

10000

V

DD

= +12V

V

SS

= 0V

V

IN

= +5V

R

L

= 10k

5

V

DD

= +12V

V

SS

= 0V

3

1800

1600

V

DD

= +12V

V

SS

= 0V

DROOP RATE – mV/s

0

1

2

3

4 5

6

7 8

INPUT VOLTAGE – Volts

9

10

1000

1400

1

0

–1

100

1200

1000

10

–3

800

600

0

1

2

3 4

5

6 7

8

INPUT VOLTAGE – Volts

9

10

0

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE – C

–5

Figure 1. Droop Rate vs. Temperature

Figure 2. Droop Rate vs. Input

Voltage (T

A

= +25

°

C)

Figure 3. Droop Rate vs. Input

Voltage (T

A

= +125

°

C)

3

2

T

A

= +25 C

V

DD

= +12V

V

SS

= 0V

HOLD STEP – mV

3

2

7

V

DD

= +12V

V

SS

= 0V

V

IN

= +5V

T

A

= +25 C

V

SS

= 0V

6

1

SLEW RATE – V/ s

HOLD STEP – mV

0

–SR

5

0

–1

+SR

4

–2

–3

0

1

2

3

4

5

6

7 8

INPUT VOLTAGE – Volts

9

10

–2

–3

–55 –35 –15

5 25 45 65 85 105 125

TEMPERATURE – C

3

10

11

12

13 14

15

V

DD

– Volts

16

17

18

Figure 4. Hold Step vs. Input Voltage

Figure 5. Hold Step vs. Temperature

Figure 6. Slew Rate vs. V

DD

2

1

V

DD

= +12V

V

SS

= 0V

OFFSET VOLTAGE – mV

20

15

10

5

0

–5

–10

R

L

= 10k

–15

–20

R

L

=

V

DD

= +12V

V

SS

= 0V

4

2

V

DD

= +12V

V

SS

= 0V

R

L

=

0

R

L

= 20k

–2

–4

–6

–8

–10

0

1

2

3

4

5

6

7 8

INPUT VOLTAGE – Volts

9

10

0

1

2

3 4

5

6

7 8

INPUT VOLTAGE – Volts

9

10

R

L

= 10k

OFFSET VOLTAGE – mV

0

R

L

=

R

L

= 20k

R

L

= 20k

–1

–2

R

L

= 10k

–3

–4

0

1

2

3 4

5

6 7

8

INPUT VOLTAGE – Volts

9

10

Figure 7. Offset Voltage vs. Input

Voltage (T

A

= +25

°

C)

Figure 8. Offset Voltage vs. Input

Voltage (T

A

= +125

°

C)

REV. D

–5–

OFFSET VOLTAGE – mV

Figure 9. Offset Voltage vs. Input

Voltage (T

A

= –55

°

C)

参数名称	属性值
功能数量	4
端子数量	16
最大供电/工作电压	8.5 V
最大工作温度	85 Cel
最小工作温度	-40 Cel
额定供电电压	5 V
最大负供电电压	-8.5 V
额定负供电电压	-5 V
加工封装描述	SOIC-16
状态	ACTIVE
工艺	CMOS
包装形状	RECTANGULAR
包装尺寸	SMALL OUTLINE
表面贴装	Yes
端子形式	GULL WING
端子间距	1.27 mm
端子涂层	TIN LEAD
端子位置	DUAL
包装材料	PLASTIC/EPOXY
温度等级	INDUSTRIAL
放大器类型	SAMPLE AND HOLD CIRCUIT
最大下降率	0.0250 V/s
最大采集时间	11 us
额定采集时间	9 us
模拟输入电压最大值	7.5 V
模拟输入电压最小值	-7.5 V
采样保持和跟踪保持	SAMPLE

	SMP04	SMP04EPZ
描述	4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, PDSO16	IC OPAMP SAMPLE HOLD 16DIP
放大器类型	SAMPLE AND HOLD CIRCUIT	采样和保持

SMP04

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