TH7301
Dual-Channel Programmable
Low-Pass Filter
Description
The device incorporates two matching 4th-order
Butterworth filters with voltage gain control to
perform low-pass filtering on quadrature demo-
dulated signals. The cutoff frequency and inband
gain are programmable via a standard 3-wire
interface. The cutoff frequency can be set between
0.8 MHz and 22.4 MHz and the inband voltage
gain can be set between -3 dB and 20 dB. The
cutoff frequency value is determined via a 10-bit
control word, with smaller step sizes in the lower
portion of the cutoff frequency range. The device
contains an on-chip oscillator to adjust the cutoff
frequency. Maintaining amplifiers configure the
Butterworth filter as the phase shift component of
the oscillator. The frequency of oscillation tracks
the filter cutoff frequency. The cutoff frequency of
the filter can be accurately set according to the
resolution of the IC by measuring the frequency of
oscillation.
Features
Y
Wide cutoff frequency range (0.8 MHz to
Y
Y
22.4 MHz)
Dual-channel architecture produces superior
matching and ease of use for quadrature signals
Companding design provides higher resolution at
lower cutoff frequencies
Y
Low power consumption (<105 mA, typical 55 mA
Y
Y
Y
from -5 V supply; Fc = 1 MHz @ 25°C)
Single ended or differential input operation
possible (AC coupled)
No external components for trimming necessary
Small package (16-pin SOP)
Applications
Y
Digital Broadcasting Systems (DBS) and
Y
Y
Microwave point to point links
Digital Video Broadcasting (DVB)
Satellite and cable TV decoders
Block Diagram
Fixed Gain
4th Order
Butterworth
Filter
4th Order
Butterworth
Filter
Fixed Gain
Figure 1: Block Diagram
Rev. 2.1
November 1999
TH7301 Dual-Channel Programmable Low-Pass Filter
Theory of
Operation
The IC is divided into I and Q channel signal
paths each consisting of an input stage, gyrator
4th order Butterworth low-pass filter, output stage
and feedback amplifier for an oscillator. A serial
interface is provided to allow the gain and cutoff
frequency to be programmed via a standard 3
wire interface. The digital cutoff frequency setting
is converted to a current by a digital-to-analog
converter. Internal bandgap references and
biasing blocks provide top level biasing on voltage
and current references for the complete device.
Input stage
The device incorporates programmable attenua-
tion in the input stages to maintain filter linearity
and to provide overall gain control for the IC. The
attenuation can be programmed in coarse steps
of 3 dB with fine control of 0.5 dB in the input
transconductor of the gyrator filters. Internal
multiplexers and back to back followers allow
single-ended or differential input operation on both
I and Q signal paths.
4th order Butterworth filter
The filter architecture is based on a fully balanced
continuous time gyrator technique with 4th order
Butterworth response. Linear current programm-
able transconductance elements are used to
synthesise the two inductors and source and
termination impedance of the filter. A termination
to source impedance ratio of 2:1 is selected to
minimise output noise while maintaining a
realisable range of capacitor values.
The use of a differential architecture has three
distinct advantages. Firstly the ultimate noise
rejection is substantially better than that of the
unbalanced LC filter. Secondly differential drive
allows the use of a current programmable Gm
stage with very much greater signal handling. And
finally DC loading of the output is common mode
and does not lead to differential DC offsets. This
last point is especially important as the bias
current within the filter can become very low at
low cutoff frequencies.
Output stage
The output stage is designed to carry out differential
to single ended conversion and provides the
capability of driving up to 15 pF of capacitive load.
Oscillator
The maintaining and limiting amplifier is used as
part of a phase shift oscillator circuit with the
gyrator Butterworth filter as the phase shift
element. The frequency of oscillation occurs at the
-3 dB frequency of the filter as the phase shift
through a 4th order Butterworth filter is 180
degrees at the -3 dB point. Voltage limiters are
integrated into the gyrator filters and limit the
differential voltage to 50 mVpp in order to ensure
that the transconductance elements remain in
their linear region of operation and hence the
expected inductance values are synthesised.
Serial interface
The filter cutoff frequency and gain are programm-
ed via a 3 wire serial interface bus. The interface
consists of the serial data clock (SCLK), serial
data input (SDATA) and a serial enable (SDEN).
The filter is programmed by asserting SDEN and
clocking the 8 bit serial data, MSB first, into the
shift register. The two most significant bits
represent the register address bits. The 6 LSB of
data are loaded into the relevant register on the
falling edge of SDEN.
The serial interface consists of: an 8 bit serial
input to parallel output (SIPO) register, three 6-bit
parallel load registers and register address
decode logic.
Once SDEN is asserted, data is clocked into the
SIPO on the positive edge of SCLK. When the
data is loaded, the two address bits are decoded
to determine which register should be updated.
The data is transfered to the register on the falling
edge of SDEN.
The serial interface does not contain a power on
reset, thus all three registers must be programmed
before reliable filter operation can be achieved.
DAC
The digital-to-analog converter is used to select
the filter cutoff frequency via a programmable
reference current. The fully companding DAC
divides the frequency range into 5 chords, each
with 128 equal frequency steps. The reference
current is programmed by an external resistor
placed between RDAC and Vee. The final output
is mirrored for the I and Q channels to provide
isolation.
The chords are selected by a 3 bit word and the
frequency step by a 7 bit word. The companding
law is generated by adding the chord currents and
dividing the required chord into 128 step currents.
2
TH7301 Dual-Channel Programmable Low-Pass Filter
Pinout
Information
The TH7301 is contained in a plastic 16 pin SOP package.
Figure 2: Pinout Schematic
Pin Definition List
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
VCCI
IIN
IREF
VDD
VSS
QREF
QIN
VCCQ
QOUT
VEEQ
RDAC
SDEN
SCLK
SDATA
VEEI
IOUT
Function
I channel positive supply
I channel signal input
I channel signal reference
Digital positive supply
Digital negative supply
Q channel signal reference
Q channel signal input
Q channel positive supply
Q channel output
Q channel negative supply
DAC reference current setting resistor connects between this pin and negative rail
Serial data enable
Serial data clock
Serial data input
I channel negative supply
I channel output
3
TH7301 Dual-Channel Programmable Low-Pass Filter
Serial Interface
Programming
The serial interface is a 3-wire bus used to
program the filter cutoff frequency and voltage
gain. Pin SDATA is the serial data input for an 8-
bit shift register, SCLK is the shift register clock
(active positive edge), SDEN (active high) is the
serial interface enable. Note that logic levels are
referenced to a - 5 V supply and that there is no
global reset for the logic devices, so a reset word
should be input after power up.
The timing diagram for the interface is shown
below.
Figure 3: Serial Interface Timing Diagram
Operating
conditions
for the 3 wire
interface
Parameter
Power supply voltage
High level input voltage
Low level input voltage
Serial data clock period
Serial data setup time
Serial data hold time
Serial data enable delay time
Serial data enable hold time
Notes:
Symbol
VSS
VIH
VIL
tCLK
tSD
tHD
tDEN
tHEN
Min
-5.25
0.3 * VSS
VSS - 0.1V
50
10
10
20
20
Typ
-5.0
Max
-4.75
VDD + 0.1V
0.7 * VSS
Unit
V
Comments
relative to VDD
note
note
ns
ns
ns
ns
ns
Logic threshold levels for inputs SCLK, SDATA and SDEN. Note that this is a negative supply IC.
The serial data is stored in one of 3 internal
registers - gain control, frequency select A and
frequency select B.
The first two bits of the serial data form an
address code for the registers. The gain control
bits AC(5...0) are decoded to select a voltage gain
between 0 dB and 20.5 dB in 0.5 dB steps. The
frequency select bits FC(2...0) select one of the
octave chords while FS(6...0) select the step
within each chord.
Address Bits
Usage
D7
Frequency Select A
Frequency Select B
Gain Control
0
0
1
D6
0
1
1
Additional bit OS0 (active high) controls the
oscillator (for test issues only). The table below
shows the address and data decoding of the serial
data input.
The serial interface does not contain a power on
reset, thus all three registers must be pro-
grammed after power on to prevent undefined
logical states and to achieve reliable filter opera-
tion. I. e. a first reset word may reset all registers
to 0.
Data Bits
D5
FS2
OS0
AC5
D4
FS1
0
AC4
D3
FS0
FS6
AC3
D2
FC2
FS5
AC2
D1
FC1
FS4
AC1
D0
FC0
FS3
AC0
4
TH7301 Dual-Channel Programmable Low-Pass Filter
Definition of
Terms
f
cset
f
c
f
step
A
v
-
-
-
-
cutoff frequency setting
cutoff frequency (-3dB bandwidth)
step size
voltage gain
The tables below show the selectable frequency
settings.
FC
(2..0)
000
001
010
011
1xx
Frequency range
fmin ... fmax (MHz)
0.8 ... 1.5937
1.6 ... 3.1875
3.2 ... 6.375
6.4 ... 12.75
12.8 ... 25.5
Step size
fstep (kHz)
6.25
12.5
25
50
100
Frequency
Setting
To maintain frequency resolution at low frequen-
cies a companding law is applied to the fre-
quency code. The frequency range is selected as
one of the five octaves in the total filter range
controlled by bits FC(2...0). Each octave is divided
linearly into 128 equally sized steps decoded by
bits FS(6...0). This frequency range is for an
external resistor value of 4.5 kΩ between pin
RDAC and VEE. The range is designed to
guarantee 0.8 MHz to 22.4 MHz cutoff range,
taking process variations in top account without
the need to change this external resistor. If there
is a need to fine tune this frequency range for any
reason, it may be re-centered by selecting a
suitably valued external resistor.
The 128 steps within each octave are decoded by
FS(6...0). The according control mechanism
applies identically to all octaves refering to the
appropriate step sizes of each octave, as shown
in the tables and the example below.
Example:
FC(2...0) = 000
(frequency range 0.8 ... 1.5937 MHz,
Step size = 6.25 kHz)
FS(6...0) = 0000011
f
cset
= 0.81875 MHz
FS
(6...0)
0000000
0000001
0000010
0000011
.
.
.
Step N
0
1
2
3
.
.
.
Cutoff Frequency
fcset = fmin + N*fstep
(MHz)
fcset = fmin
fcset = fmin + fstep
fcset = fmin + 2*fstep
fcset = fmin + 3*fstep
.
.
.
1111111
127
fcset = fmin + 127*fstep
Gain Setting
The gain control bits AC(5...0) are decoded to
select a voltage gain between -3 dB and 20.5 dB
in 0.5 dB steps. The gain control is divided into 8
steps controlled by AC(2...0) with additive step
sizes of 0.5 dB decoded by AC(5...3).
For example, to set the gain to 16 dB
AC(5...0) = 011001.
The table below shows the gain setting.
AC(2...0)
000
001
010
011
100
101
110
111
Gain (dB)
18
15
12
9
6
3
0
-3
AC(5...3)
000
001
010
011
100
101
110
111
Gain (dB)
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.0
5
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