M
.tec
1M x 16Bit x 4 Banks synchronous DRAM
TBS6416B4E
GENERAL DESCRIPTION
The TBS6416B4E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,
fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
•
JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four-banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
ORDERING INFORMATION
Part No.
TBS6416B4E-7G
Max Freq.
143MHz
Interface
LVTTL
Package
54
TSOP(II)
Revision_1.1
1
TwinMOS Technologies Inc.
Sep. 2000
M
.tec
PIN CONFIGURATION
(Top View)
TBS6416B4E
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
Revision_1.1
2
TwinMOS Technologies Inc.
Sep. 2000
M
.tec
PIN FUNCTION DESCRIPTION
Pin Name
A0~ A11
BS0, BS1
DQ0 ~DQ15
/CS
/RAS
/CAS
/WE
UDQM/LDQM
CLK
CKE
Vcc
Vss
Vcc
Vss
NC
Address
Bank
Data Input / Output
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Input /output mask
Clock Input
Clock Enable
Power (+3.3 V)
Ground
TBS6416B4E
Function
Description
Multiplexed pins for row and column address Row address: A0~ A11.
Column address: A0 ~ A7.
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
Command input. When sampled at the rising edge of the clock, /RAS,
/CAS and /WE define the operation to be executed.
Referred to /RAS
Referred to /RAS
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Q Power (+ 3.3 V) for I/O Separated power from
VCC
, used for output buffers to improve noise.
buffer
Q Ground for I/O buffer
No Connection
Separated ground from
VSS
, used for output buffers to improve noise.
No connection
Revision_1.1
3
TwinMOS Technologies Inc.
Sep. 2000
M
.tec
FUNCTIONAL BLOCK DIAGRAM
TBS6416B4E
Bank Select
Data Input
Sense AMP
Address
ADD
Buffer
Row Decoder
&
Refresh Counter
1Mx16
1Mx16
1Mx16
1Mx16
Column Decoder
Output Buffer
DQ
Column Buffer
/CS
/ RAS
/ CAS
/ WE
CLK
CKE
Commend
Decoder
&
Clock
Buffer
Latency &
Burst Length
Programming
Register
Revision_1.1
4
TwinMOS Technologies Inc.
Sep. 2000
M
.tec
ABSOLUTE MAXIMUM RATING
Parameter
Voltage on any pin relative to V
SS
Voltage on VCC supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
TBS6416B4E
Symbol
V
IN
, V
OUT
VCC, VCC
Q
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
℃
W
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to
the
recommended operating conditions.
Exposure to higher voltage
than recommended
for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current (Input)
Input leakage current (I/O pins)
Symbol
VCC, VCC
Q
V
IH
V
IL
V
OH
V
OL
I
IL
I
IL
Min
3.0
2.0
-0.3
2.4
-
-1
-1.5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
VCC
Q
+0.3
0.8
-
0.4
1
1.5
Unit
V
V
V
V
V
uA
uA
Note
1
2
I
OH
=-2mA
I
OL
=2mA
3
3,4
Notes:
1.
V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≦
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≦
3ns.
3. Any input 0V
≦
V
IN
≦
VCC
Q,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. D
out
is disabled, 0V
≦
V
out
≦
VCC
Q
Revision_1.1
5
TwinMOS Technologies Inc.
Sep. 2000
Microchip MCU
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