19-2959; Rev 3; 5/04
KIT
ATION
EVALU
BLE
AVAILA
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
General Description
Features
o
High Resolution
MAX1494: 4.5 Digits (±19,999 Count)
MAX1492: 3.5 Digits (±1999 Count)
o
Sigma-Delta ADC Architecture
No Integrating Capacitors Required
No Autozeroing Capacitors Required
>100dB of Simultaneous 50Hz and 60Hz
Rejection
o
Operate from a Single 2.7V or 5.25V Supply
o
Selectable Input Range of ±200mV or ±2V
o
Selectable Voltage Reference: Internal 2.048V
or External
o
Internal High-Accuracy Oscillator Needs No
External Components
o
Automatic Offset Calibration
o
Low Power
Maximum 960µA Operating Current
Maximum 400µA Shutdown Current
o
Small 32-Pin 7mm x 7mm TQFP Package
(4.5 Digits), 28-Pin SSOP Package (3.5 Digits)
o
Triplexed LCD Driver
o
SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
o
Evaluation Kit Available (Order MAX1494EVKIT)
MAX1492/MAX1494
The MAX1492/MAX1494 low-power, 3.5- and 4.5-digit,
analog-to-digital converters (ADCs) with integrated liquid
crystal display (LCD) drivers operate from a single 2.7V
to 5.25V power supply. They include an internal refer-
ence, a high-accuracy on-chip oscillator, and a triplexed
LCD driver. An internal charge pump generates the neg-
ative supply needed to power the integrated input buffer
for single-supply operation. The ADC is configurable for
either a ±2V or ±200mV input range and outputs its con-
version results to an LCD and/or to a microcontroller
(µC). µC communication is facilitated through an
SPI™-/QSPI™-/MICROWIRE™-compatible serial inter-
face. The MAX1492 is a 3.5-digit (±1999 count) device,
and the MAX1494 is a 4.5-digit (±19,999 count) device.
The MAX1492/MAX1494 do not require external-preci-
sion integrating capacitors, autozero capacitors, crystal
oscillators, charge pumps, or other circuitry required
with dual-slope ADCs (commonly used in panel meter
circuits).
These devices also feature on-chip buffers for the dif-
ferential signal and reference inputs, allowing direct
interface with high-impedance signal sources. In addi-
tion, they use continuous internal-offset calibration and
offer >100dB simultaneous rejection of 50Hz and 60Hz
line noise. Other features include data hold and peak
hold, overrange and underrange detection, and a low-
battery monitor.
The MAX1494 comes in a 32-pin, 7mm x 7mm TQFP
package, and the MAX1492 comes in 28-pin SSOP and
28-pin PDIP packages. All devices in this family operate
over the 0°C to +70°C commercial temperature range.
Applications
Digital Panel Meters
Hand-Held Meters
Digital Voltmeters
Digital Multimeters
PART
MAX1492CAI
MAX1492CNI
MAX1494CCJ
Ordering Information
TEMP
RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-
PACKAGE
28 SSOP
28 PDIP
32 TQFP
RESOLUTION
(DIGITS)
3.5
3.5
4.5
Pin Configurations appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
MAX1492/MAX1494
ABSOLUTE MAXIMUM RATINGS
AV
DD
to GND............................................................-0.3V to +6V
DV
DD
to GND ...........................................................-0.3V to +6V
AIN+, AIN- to GND................................V
NEG
to +(AV
DD
+ 0.3V)
REF+, REF- to GND...............................V
NEG
to +(AV
DD
+ 0.3V)
LOWBATT to GND ...................................-0.3V to (AV
DD
+ 0.3V)
CLK,
EOC, CS,
DIN, SCLK, DOUT to
GND .....................................................-0.3V to (DV
DD
+ 0.3V)
SEG_ and BP_ to GND ............................-0.3V to (DV
DD
+ 0.3V)
V
NEG
to GND ...........................................-2.6V to (AV
DD
+ 0.3V)
V
DISP
to GND ...........................................-0.3V to (DV
DD
+ 0.3V)
Maximum Current into Any Pin ...........................................50mA
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ...........762mW
28-Pin PDIP (derate 14.3mW/°C above +70°C)......1142.9mW
32-Pin TQFP (derate 20.7mW/°C above +70°C).....1652.9mW
Operating Temperature Range...............................0°C to +70°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= DV
DD
= +2.7V to +5.25V, GND = 0, V
REF+
- V
REF-
= 2.048V (external reference). Internal clock mode, unless otherwise noted.
All specifications are at T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.)
PARAMETER
DC ACCURACY
Noise-Free Resolution
Integral Nonlinearity (Note 1)
Range Change Accuracy
Rollover Error (See the
Definitions
Section)
Output Noise
Offset Error (Zero Input Reading)
Gain Error
Offset Drift (Zero-Reading Drift)
Gain Drift
INPUT CONVERSION RATE
External Clock Frequency
External-Clock Duty Cycle
Conversion Rate
Internal clock
External clock, f
CLK
= 4.915MHz
RANGE bit = 0, ±2V
RANGE bit = 1, ±200mV
-2.0
-0.2
-2.2
40
5
5
+2.0
+0.2
+2.2
4.915
60
MHz
%
Hz
Offset
V
IN
= 0 (Note 2)
(Note 3)
V
IN
= 0 (Note 4)
-0
-0.5
0.1
±1
INL
MAX1494
MAX1492
2.000V range
200mV range
(V
AIN+
- V
AIN-
= 0.100V) on 200mV range /
(V
AIN+
- V
AIN-
= 0.100V) on 2.0V range
V
AIN+
- V
AIN-
= full scale,
V
AIN-
- V
AIN+
= full scale
-19,999
-1999
±1
±1
10:1
±1
10
0
+0.5
+19,999
+1999
Count
Count
Ratio
Count
µV
P-P
Reading
%FSR
µV/°C
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (AIN+, AIN-, bypass to GND with 0.1µF or greater capacitors)
AIN Input-Voltage Range
(Note 5)
AIN Absolute Input Voltage to
GND
V
V
2
_______________________________________________________________________________________
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= +2.7V to +5.25V, GND = 0, V
REF+
- V
REF-
= 2.048V (external reference). Internal clock mode, unless otherwise noted.
All specifications are at T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.)
PARAMETER
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
Common-Mode Rejection
Input Leakage Current
Input Capacitance
Dynamic Input Current
LOWBATT TripThreshold
LOWBATT Leakage Current
Hysteresis
INTERNAL REFERENCE (INTREF BIT = 1, REF- = GND, bypass REF+ to GND with a 4.7µF capacitor)
REF Output Voltage
REF Output Short-Circuit Current
REF Output Temperature
Coefficient
Load Regulation
Line Regulation
Noise Voltage
0.1Hz to 10Hz
10Hz to 10kHz
Differential (V
REF+
- V
REF-
)
-2.2
Internal clock mode, 50Hz and 60Hz ±2%
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
Common-Mode Rejection
Input Leakage Current
Input Capacitance
Dynamic Input Current
(Note 6)
-20
CMR
CMR
External clock mode, 50Hz and 60Hz ±2%,
f
CLK
= 4.915MHz
For 50Hz and 60Hz ±2%, R
SOURCE
< 10kΩ
At DC
100
120
150
100
10
10
+20
dB
TC
VREF
AV
DD
= 5V
I
SOURCE
= 0 to 300µA, I
SINK
= 0 to 30µA
V
REF
AV
DD
= 5V, T
A
= +25°C
2.007
2.048
1
40
6
50
25
400
2.048
+2.2
2.089
V
mA
ppm/°C
mV/µA
µV/V
µV
P-P
(Note 6)
-20
2.048
10
20
LOW-BATTERY VOLTAGE MONITOR (LOWBATT)
V
pA
mV
CMR
CMR
SYMBOL
CONDITIONS
Internal clock mode, 50Hz and 60Hz ±2%
External clock mode, 50Hz and 60Hz ±2%,
f
CLK
= 4.915MHz
For 50Hz and 60Hz ±2%, R
SOURCE
< 10kΩ
At DC
MIN
TYP
100
120
150
100
10
10
+20
dB
MAX
UNITS
MAX1492/MAX1494
dB
dB
nA
pF
nA
EXTERNAL REFERENCE (INTREF BIT = 0, bypass REF+ and REF- to GND with 0.1µF or larger capacitors)
REF Input Voltage
Absolute REF Input Voltage to
GND
V
V
dB
dB
nA
pF
nA
_______________________________________________________________________________________
3
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
MAX1492/MAX1494
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= +2.7V to +5.25V, GND = 0, V
REF+
- V
REF-
= 2.048V (external reference). Internal clock mode, unless otherwise noted.
All specifications are at T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.)
PARAMETER
CHARGE PUMP (C
NEG
= 0.1µF)
Output Voltage
Input Current
Input Low Voltage
Input High Voltage
Input Hysteresis
DIGITAL OUTPUTS (DOUT,
EOC)
Output Low Voltage
Output High Voltage
Tri-State Leakage Current
Tri-State Output Capacitance
POWER SUPPLY
AV
DD
Voltage
DV
DD
Voltage
Power-Supply Rejection AV
DD
Power-Supply Rejection DV
DD
AV
DD
Current (Notes 8, 9)
AV
DD
DV
DD
PSRR
A
PSRR
D
I
AVDD
(Note 7)
(Note 7)
AV
DD
= 5V
Standby
DV
DD
= 5V
DV
DD
Current (Notes 8, 9)
LCD DRIVER
MAX1492
RMS Segment On Voltage
MAX1494
MAX1492
RMS Segment Off Voltage
MAX1494
Display Voltage Setup Resistor
Display Multiplex Rate
LCD Data-Update Rate
R
DISP
MAX1494 only
1.92 x
DV
DD
1.92 x
(DV
DD
- V
DISP
)
1/3 x
DV
DD
1/3 x
(DV
DD
- V
DISP
)
157.5
107
2.5
I
DVDD
DV
DD
= 3.3V
Standby
2.70
2.70
80
100
580
240
260
130
10
660
380
320
180
20
µA
5.25
5.25
V
V
dB
dB
µA
V
OL
V
OH
I
L
C
OUT
I
SINK
= 1mA
I
SOURCE
= 200µA
D
OUT
only
D
OUT
only
0.8 x DV
DD
-10
15
+10
0.4
V
V
µA
pF
V
NEG
I
IN
V
INL
V
INH
V
HYST
DV
DD
= 3.0V
0.7 x DV
DD
200
V
IN
= 0 or DV
DD
-2.60
-10
-2.42
-2.30
+10
0.3 x
DV
DD
V
µA
V
V
mV
DIGITAL INPUTS (SCLK, DIN,
CS,
CLK)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
kΩ
Hz
Hz
4
_______________________________________________________________________________________
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
TIMING CHARACTERISTICS (Notes 10, 11 and Figure 13)
(AV
DD
= DV
DD
= 2.7V to +5.25V, GND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
SCLK Fall to DOUT Valid
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
SYMBOL
f
SCLK
t
CH
t
CL
t
DS
t
DH
t
CSS
t
CSH
t
DO
t
TR
t
DV
C
LOAD
= 50pF (Figures 18, 19)
C
LOAD
= 50pF (Figures 18, 19)
C
LOAD
= 50pF (Figures 18, 19)
CONDITIONS
MIN
0
100
100
50
0
50
0
120
120
120
TYP
MAX
4.2
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX1492/MAX1494
Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
and offset error.
Note 2:
Offset calibrated. See the
OFFSET_CAL1
and
OFFSET_CAL2
sections in the
On-Chip Registers
section.
Note 3:
Offset nulled.
Note 4:
Drift error is eliminated by recalibration at the new temperature.
Note 5:
The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6:
V
AIN+
or V
AIN-
= -2.2V to +2.2V. V
REF+
or V
REF-
= -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7:
Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8:
CLK and SCLK are idle.
Note 9:
Power-supply currents are measured with all digital inputs at either GND or DV
DD
and with the device in internal clock mode.
Note 10:
All input signals are specified with t
RISE
= t
FALL
= 5ns (10% to 90% of DV
DD
) and are timed from a voltage level of 50% of
DV
DD
, unless otherwise noted.
Note 11:
See the serial-interface timing diagrams.
Note 1:
_______________________________________________________________________________________
5
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