SSM4532M
COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Simple drive requirement
D2
N-ch
D2
D1
D1
G2
S2
BV
I
D
DSS
+30V
50mΩ
+5A
-30V
70mΩ
-4A
Low on-resistance
Fast switching
R
DS(ON)
P-ch
BV
DSS
R
DS(ON)
I
D
SO-8
S1
G1
Description
MOSFETs from
Silicon Standard Corp.
provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-
effectiveness.
The SO-8 package is
widely
preferred for commercial
and
industrial surface mount applications and
is well
suited for
low-voltage
applications such as DC/DC converters.
G1
D1
D2
G2
S1
S2
Absolute Maximum Ratings
Symbol
V
DS
V
GS
I
D
@ T
A
=25°C
I
D
@ T
A
=70°C
I
DM
P
D
@ T
A
=25°C
T
STG
T
J
Parameter
Drain-Source Voltage
Gate-Source Voltag
Continuous Drain Current
3
Continuous Drain Current
3
Pulsed Drain Current
1,4
Total Power Dissipation
Linear Derating Factor
Storage Temperature Range
Operating Junction Temperature Range
+30
±20
+5
+4
+20
2.0
0.016
-55 to 150
-55 to 150
Rating
N-channel
P-channel
-30
±20
-4
-3.2
-20
V
V
A
A
A
W
W/°C
°C
°C
Units
Thermal Data
Symbol
Rthj-amb
Parameter
Thermal Resistance Junction-ambient
Max.
Value
62.5
Unit
°C/W
Rev.2.01 7/01/2004
www.SiliconStandard.com
1 of 11
SSM4532M
N-channel Electrical Characteristics @ T
j
=25
o
C (unless otherwise specified)
Symbol
BV
DSS
Parameter
Drain-Source Breakdown Voltage
Test Conditions
V
GS
=0V, I
D
=250uA
Min.
30
-
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
0.037
Max. Units
-
-
50
70
3
-
1
25
±100
20
-
-
12
18
30
12
360
210
80
V
V/°C
mΩ
mΩ
V
S
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
∆
BV
DSS
/
∆
Tj
R
DS(ON)
Breakdown Voltage Temperature Coefficient
Reference to 25°C, I
D
=1mA
Static Drain-Source On-Resistance
V
GS
=10V, I
D
=5A
V
GS
=4.5V, I
D
=4.2A
-
-
-
8
-
-
-
10.2
1.2
3.4
6
9
15
5.5
240
145
55
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current (T
j
=25
o
C)
Drain-Source Leakage Current (T
j
=55
o
C)
V
DS
=V
GS
, I
D
=250uA
V
DS
=10V, I
D
=5A
V
DS
=30V, V
GS
=0V
V
DS
=24V, V
GS
=0V
V
GS
=±20V
I
D
=5A
V
DS
=10V
V
GS
=10V
V
DS
=10V
I
D
=1A
R
G
=6Ω,V
GS
=10V
R
D
=10Ω
V
GS
=0V
V
DS
=25V
f=1.0MHz
Gate-Source Leakage
Total Gate Charge
2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time
2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Source-Drain Diode
Symbol
I
S
I
SM
V
SD
Parameter
Continuous Source Current ( Body Diode )
Test Conditions
V
D
=V
G
=0V , V
S
=1.2V
T
j
=25°C, I
S
=1.7A, V
GS
=0V
Min.
-
-
-
Typ.
-
-
0.8
Max. Units
1.7
20
1.2
A
A
V
Pulsed Source Current ( Body Diode )
1
Forward On Voltage
2
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on FR4 board, t<10sec.
4.Pulse width <10us , duty cycle <1%.
Rev.2.01 7/01/2004
www.SiliconStandard.com
2 of 11
SSM4532M
P-channel Electrical Characteristics @ T
j
=25
o
C (unless otherwise specified)
Symbol
BV
DSS
Parameter
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Test Conditions
V
GS
=0V, I
D
=250uA
Reference to 25°C, I
D
=-1mA
V
GS
=-10V, I
D
=-4A
V
GS
=-4.5V, I
D
=-3A
V
DS
=V
GS
, I
D
=-250uA
V
DS
=-10V, I
D
=-4A
V
DS
=-30V, V
GS
=0V
V
DS
=-24V, V
GS
=0V
V
GS
=
±
20V
I
D
=-4A
V
DS
=-10V
V
GS
=-10V
V
DS
=-10V
I
D
=-1A
R
G
=6Ω
,V
GS
=-10V
R
D
=10Ω
V
GS
=0V
V
DS
=-25V
f=1.0MHz
Min.
-30
-
-
-
-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
-0.028
Max. Units
-
-
70
90
-3
-
-1
-25
±100
36
-
-
16
18
40
20
1140
518
135
V
V/°C
mΩ
mΩ
V
S
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
∆
BV
DSS
/
∆
Tj
R
DS(ON)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Static Drain-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current (T
j
=25
o
C)
Drain-Source Leakage Current (T
j
=55
o
C)
-
-
-
5
-
-
-
18.3
3.6
1.5
8
9
21
10
760
345
90
Gate-Source Leakage
Total Gate Charge
2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time
2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Source-Drain Diode
Symbol
I
S
I
SM
V
SD
Parameter
Continuous Source Current ( Body Diode )
Test Conditions
V
D
=V
G
=0V , V
S
=-1.2V
T
j
=25°C, I
S
=-1.7A, V
GS
=0V
Min.
-
-
-
Typ.
-
-
-
Max. Units
-1.7
-20
-1.2
A
A
V
Pulsed Source Current ( Body Diode )
1
Forward On Voltage
2
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on FR4 board, t<10sec.
4.Pulse width <10us , duty cycle <1%.
Rev.2.01 7/01/2004
www.SiliconStandard.com
3 of 11
SSM4532M
N-channel
70
50
T
C
=25
o
C
60
V
G
=10V
40
T
C
=150
o
C
V
G
=10V
V
G
=8.0V
50
I
D
, Drain Current (A)
I
D
, Drain Current (A)
V
G
=8.0V
30
40
V
G
=6.0V
V
G
=6.0V
20
30
20
V
G
=4.0V
10
V
G
=4.0V
V
G
=3.0V
10
V
G
=3.0V
0
0
1
2
3
4
5
6
7
8
9
0
0
1
2
3
4
5
6
7
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
85
1.8
75
Id=5A
T
c
=25°C
1.6
I
D
=5A
V
G
=10V
R
DSON
(mΩ )
65
Normalized R
DS(ON)
3
4
5
6
7
8
9
10
11
1.4
1.2
55
1.0
45
0.8
35
0.6
-50
0
50
100
150
V
GS
(V)
T
j
, Junction Temperature (
o
C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
Rev.2.01 7/01/2004
www.SiliconStandard.com
4 of 11
SSM4532M
N-channel
6
3
5
I
D
, Drain Current (A)
4
2
3
P
D
(W)
1
0
25
50
75
100
125
150
0
50
100
150
2
1
0
T
c
, Case Temperature (
o
C)
T
c
,Case Temperature ( C)
o
Fig 5. Maximum Drain Current vs.
Fig 6. Typical Power Dissipation
Case Temperature
100
1
DUTY=0.5
Normalized Thermal Response (R
thja
)
0.2
10
0.1
0.1
0.05
I
D
(A)
0.02
10us
1
0.01
P
DM
100us
1ms
T
c
=25 C
Single Pulse
o
0.01
t
T
SINGLE PULSE
Duty factor = t/T
Peak T
j
= P
DM
x R
thja
+ T
a
10ms
100ms
0.001
10
100
0.1
0.1
1
0.0001
0.001
0.01
0.1
1
10
100
1000
V
DS
(V)
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
Rev.2.01 7/01/2004
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5 of 11
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