CXA3503R
Driver/Timing Generator for Color LCD Panels
Description
The CXA3503R is an IC designed to drive the color
LCD panels LCX032 and LCX033.
This IC greatly reduces the number of peripheral
circuits and parts by incorporating a RGB driver and
timing generator for video signals onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various settings to
be performed by microcomputer control, etc.
Features
•
Color LCD panel LCX032 and LCX033 driver
•
Supports NTSC and PAL systems
•
Supports 16:9 wide display (letter box and pulse
elimination display)
•
Supports Y/color difference and RGB inputs
•
Supports OSD input (digital input)
•
Power saving function
•
Serial interface circuit
•
Electronic attenuators (D/A converter)
•
Trap and LPF (f0, fc variable)
•
COMMON output circuits
•
Sharpness function
•
2-point
γ
correction circuit
•
R, G, B signal delay time adjustment circuit
•
D/A output pin (0 to 3V, 8 level output)
•
Output polarity inversion circuit
•
Supports AC drive for LCD panel during no signal
Applications
Color LCD viewfinders
Absolute Maximum Ratings
(Ta = 25°C)
•
Supply voltage V
CC
1
6
V
V
CC
2
15
V
V
CC
3
15
V
V
DD
5.5
V
•
Analog input pin voltage
VINA (Pins 57, 58 and 59)
GND – 0.3 to V
CC
1 + 0.3 V
VINA (Pins 3, 69)
V
CC
1
V
VINA (Pin 30)
1.5 to V
CC
2 – 4
V
VINA (Pin 71)
0.9
Vp-p
VINA (Pins 70, 72)
0.8
Vp-p
72 pin LQFP (Plastic)
•
Digital input pin voltage
VIND (other than Pins 5, 10, 14, 15 and 16)
V
SS
– 0.3 to V
DD
+ 0.3 V
VIND (Pins 5, 10)
V
SS
– 0.3 to +5.5
V
•
Common input pin voltage
VINAD (Pins 14, 15 and 16)
GND, V
SS
– 0.3 to +5.5 V
•
Operating temperature
Topr
–15 to +75
°C
•
Storage temperature
Tstg
–55 to +150
°C
•
Allowable power dissipation
P
D
(Ta
≤
25°C)
737
mW
Operating conditions
•
Supply voltage
2.7 to 3.6
V
V
CC
1 – GND1
V
CC
2 – GND2
11.0 to 14.0
V
V
CC
3 – GND3
11.0 to 14.0
V
V
DD
– Vss
2.7 to 3.6
V
•
Input voltage
SIG.C voltage
VSIG.C
5.0 to 6.5
V
∗
1
RGB input signal voltage (Pins 70, 71 and 72)
VRGB
0 to 0.7 (0.5 typ.) Vp-p
Y input signal voltage (Pin 71)
∗
2
VY
0 to 0.5 (0.35 typ.) Vp-p
R-Y input voltage (Pin 72)
∗
2
VR-Y
0 to 0.49 (0.245 typ.) Vp-p
B-Y input voltage (Pin 70)
∗
2
VB-Y
0 to 0.622 (0.311 typ.) Vp-p
∗
1
During RGB input
∗
2
During Y/color difference input
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99733A98-PS
CXA3503R
Block Diagram
TST14
TST13
TST12
TST11
TST10
GND3
TST9
TST8
TST7
TST6
TST5
38
DWN
COM
54
Vss
Vcc3
POF
Vss
53
Vss
52
51
50
49
48
47
46
45
44
43
GND3
42
41
+12.0V
40
39
37
+12.0V
Buf
V
DD
55
+3.0V
OSD RGB
TST15
56
OSD B
57
OSD R
58
LPF
OSD G
59
G
BLK
60
MODE
HCK1
61
HCK2
62
Vcc1
63
+3.0V
HST
64
RGT
65
EN
66
STB
67
VCK
68
FIL IN
69
MODE
B/B-Y
70
CLK
G/Y
71
DA
R/R-Y
72
H.FILTER
Vss
1
Vss
2
FIL OUT
3
SYNC IN
4
SYNC OUT
5
CSYNC/HD
6
DA OUT
7
TST1
8
F ADJ
SYNC SEP
Buf
GND1
9
GND1
10
VD
11
VST
12
TST2
13
TST3
14
SCK
15
SEN
16
SDAT
17
R INJECT
S/P CONV
REGISTER DAC
Vss
18
V
SS
+3.0V
19
V
DD
V COUNTER
HCOUNTER
HPULSE
GEN
PICTURE
DL1
DL1
PULSE
ELM
SUB-BRIGHT
HCK
GEN
PIC-G
CLAMP
G
R
MATRIX
B
POL SW
28
TST4
HDO GEN
VDO GEN
27
HDO
26
VDO
25
XCLR
PHASE
COMPARATOR
HSYNC DET
H SKEW DET
V SEP
CK
CONTROL
24
RPD
Vss
23
Vss
22
CKI
21
CKO
MCK
+3.0V
20
V
DD
SUB-BRT R
SUB-BRT B
COM-DC
R
B
BLK-LIM
BLKLIM
SIG.C
S/H
GEN
CONTRAST
CONT
TRAP
FILTER
BIAS
GAMMA
CLAMP
S/H
LPF
FILTER USER-BRIGHT
U-BRT
γ
1
γ
2
WHITLIM
SUB-CONT R
SUB-CONT B
Buf
Buf
36
G OUT
35
G DC DET
34
R OUT
33
R DC DET
Buf
32
B OUT
31
B DC DET
30
SIG.C
GND2
29
GND2
PLL
COUNTER
PIC-F
HUE
HUE
COLOR
CLAMP
CLP
V CONTROL
V POSITION
–2–
Vcc2
Vss
CXA3503R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Symbol
V
SS
FIL OUT
SYNC IN
SYNC OUT
CSYNC/HD
DA OUT
TST1
F ADJ
GND1
VD
VST
TST2
TST3
SCK
SEN
SDAT
R INJECT
V
SS
V
DD
V
DD
CKO
CKI
V
SS
RPD
XCLR
VDO
HDO
TST4
GND2
SIG.C
B DC DET
B OUT
R DC DET
R OUT
G DC DET
G OUT
V
CC
2
I/O
—
O
I
O
I
O
—
O
—
I
O
—
—
I
I
I
O
—
—
—
O
I
—
O
I
O
O
—
—
I
O
O
O
O
O
O
—
Digital 3.0V GND
H filter output (for using internal sync separation)
Sync separation circuit input (for using internal sync separation)
Sync separation circuit output (for using internal sync separation)
CSYNC/horizontal sync signal input
DAC output
Test (Leave this pin open.)
Trap f0 adjusting resistor connection
Analog 3.0V GND
Vertical sync signal input
V start pulse output
Test (Leave this pin open.)
Test (Leave this pin open.)
Serial clock input
Serial load input
Serial data input
Serial block current controlling resistor connection
Digital 3.0V GND
Digital 3.0V power supply
Digital 3.0V power supply
Oscillation cell output
Oscillation cell input
Digital 3.0V GND
Phase comparator output
Power-on reset capacitor connection (timing generator block)
VDO pulse output
HDO pulse output
Test (Connect to GND.)
Analog 12.0V GND
R, G and B output DC voltage adjustment
B signal DC voltage feedback circuit capacitor connection
B signal output
R signal DC voltage feedback circuit capacitor connection
R signal output
G signal DC voltage feedback circuit capacitor connection
G signal output
Analog 12.0V power supply
–3–
H
L
Description
Input pin for
open status
CXA3503R
Pin
No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
TST5
TST6
TST7
V
CC
3
COM
GND3
TST8
POF
DWN
TST9
TST10
TST11
TST12
TST13
TST14
V
SS
V
SS
V
DD
TST15
OSD B
OSD R
OSD G
BLK
HCK1
HCK2
V
CC
1
HST
RGT
EN
STB
VCK
FIL IN
B/B-Y
G/Y
R/R-Y
I/O
—
—
—
—
O
—
—
O
O
—
—
—
—
—
—
—
—
—
—
I
I
I
O
O
O
—
O
O
O
O
O
I
I
I
I
Test (Leave this pin open.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Description
Input pin for
open status
Analog 12.0V COM power supply
Common pad voltage for LCD panel output
Analog 12.0V COM GND
Test (Leave this pin open.)
LCD panel power supply on/off (Leave this pin open when not using
this function.)
Right/left inversion switching signal output
Test (Connect to GND.)
Test (Connect to GND.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Digital 3.0V GND
Digital 3.0V GND
Digital 3.0V power supply
Test (Connect to GND.)
OSD B input
OSD R input
OSD G input
BLK pulse output
H clock pulse 1 output
H clock pulse 2 output
Analog 3.0V power supply
H start pulse output
Right/left inversion switching signal output
EN pulse output
STB pulse output
V clock pulse output
H filter input (for using internal sync separation)
B/B-Y signal input
G/Y signal input
R/R-Y signal input
∗
DWN: DOWN SCAN and UP SCAN, RGT: RIGHT SCAN and LEFT SCAN
H: pull-up processing, L: pull-down processing
–4–
CXA3503R
Analog Block Pin Description
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
V
CC
1
23k
Description
2
FIL OUT
2.15V
2
200
Amplifies and outputs the sync
portion of the video signal input
to FIL IN (Pin 69).
GND1
V
CC
1
3
SYNC IN
1.1V
3
200
Sync separation circuit input.
Inputs the FIL OUT (Pin 2)
output signal via a capacitor.
GND1
V
CC
1
4
SYNC OUT
—
4
Sync separation output.
Positive polarity output in open
collector format.
GND1
V
CC
1
6
DA OUT
—
6
50
GND1
50
DA output.
Outputs the serial data
converted to DC voltage. The
current driving capacity is
±1.0mA (max.).
V
CC
1
8
F ADJ
1.1V
8
10
6.5k
GND1
Connect a resistor between this
pin and GND1 to control the
internal LPF and trap
frequencies.
Connect a 33kΩ resistor
(tolerance ±2%, temperature
characteristics ±200ppm or less).
This pin is easily affected by
external noise, so make the
connection between the pin and
external resistor, and between
the GND side of the external
resistor and the GND1 pin as
close as possible.
–5–
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