Memory ICs
1,024-Bit Serial Electrically Erasable PROM
BR93LL46F / BR93LL46FV
•
Features CMOS technology
• Low power
• 64
×
16 bit configuration
• 1.8V to 4.0V operation
• Low power dissipation
– 0.5mA (typ.) active current
– 0.4µA (typ.) standby current
• Auto increment for efficient data dump
• Automatic erase-before-write
• Hardware and software write protection
– Defaults to write-disabled state at power up
– Software instructions for write-enable / disable
– Vcc lockout inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B packages
• Device status signal during write cycle
• 100,000 ERASE / WRITE cycles
• 10 years Data Retention
•
Pin assignments
N.C.
V
CC
CS
SK
1
2
3
4
8
7
6
5
(SOP8 / SSOP-B8)
N.C.
GND
DO
DI
BR93LL46F
BR93LL46FV
•
Pin descriptions
Pin Name
N.C.
V
CC
CS
SK
DI
DO
GND
N.C.
Not connected
Power supply
Chip select input
Serial clock input
Start bit, operating code, address, and
serial data input
Serial data output, READY / BUSY
internal status display output
Ground
Not connected
Function
•
Overview and BR93LL46FV are CMOS serial input / output-type memory circuits (EEPROMs) that can be
The BR93LC46F
programmed electrically. Each is configured of 64 words
×
16 bits (1,024 bits), and each word can be accessed indi-
vidually and data read from it and written to it. Operation control is performed using five types of commands. The
commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write
operation, the internal status signal (READY or BUSY) can be output from the DO pin.
1
Memory ICs
BR93LL46F / BR93LL46FV
•
Block diagram
Power supply
CS
Command decode
Control
Clock generation
voltage detector
Write
disable
High voltage
generator
SK
Address
DI
Command
register
buffer
6bit
Address
decoder
6bit
1,024-bit
Data
register
R/W
EEPROM array
16bit
AMP.
16bit
DO
Dummy bit
•
Absolute maximum ratings
Parameter
Applied voltage
Power dissipation
Storage temperature
Operating temperature
Terminal voltage
BR93LL46F
BR93LL46FV
Symbol
V
CC
Pd
Tstg
Topr
—
Limits
– 0.3 ~ + 7.0
350
∗
1
300
∗
2
– 65 ~ + 125
– 20 ~ + 70
– 0.3 ~ V
CC
+ 0.3
Unit
V
mW
°C
°C
V
∗
1 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.
∗
2 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
•
Recommended operating conditions
Parameter
Power supply voltage
Input voltage
Symbol
V
CC
V
IN
Limits
1.8 ~ 4.0
2.0 ~ 4.0
0 ~ V
CC
Unit
V
V
Conditions
Ta = 0 ~ 70°C
Ta = – 20 ~ + 70°C
—
2
Memory ICs
BR93LL46F / BR93LL46FV
CC
•
Electrical characteristics (unless otherwise noted, Ta = – 20 to + 70°C, V
Parameter
Input low level voltage
Input high level voltage
Output low level voltage 1
Output low level voltage 2
Output high level voltage 2
Input leakage current
Output leakage current
Operating current dissipation 1
Operating current dissipation 2
Standby current
Symbol
V
IL
V
IH
V
OL1
V
OL2
V
OH2
I
LI
I
LO
I
CC1
I
CC2
I
SB
Min.
– 0.3
0.8
×
V
CC
—
—
V
CC
–
0.3
– 1.0
– 1.0
—
—
—
Typ.
—
—
—
—
—
—
—
0.5
0.4
0.4
Max.
0.2
×
V
CC
V
CC
+
0.3
0.3
0.2
—
1.0
1.0
1.0
1.0
1.0
Unit
V
V
V
V
V
µA
µA
mA
mA
µA
= 1.8 to 4.0V)
Conditions
—
—
I
OL
= 1.0mA
I
OL
= 20µA
I
OH
= 100µA
V
IN
= 0V ~ V
CC
V
OUT
= 0V ~ V
CC
, CS = GND
V
IN
= V
IH
/ V
IL
, DO = OPEN, f
SK
= 250kHz
WRITE
V
IN
= V
IH
/ V
IL
, DO = OPEN, f
SK
= 250kHz, READ
CS = SK = DI = GND, DO = OPEN
∗
1 About the operating current dissipation
I
CC1
indicates the average current dissipation during a writing operation, and I
CC2
indicates the average current dissipation during a reading operation.
Because this is internal logic switching current, it changes based on the SK frequency.
∗
2 About the standby current
This is the current dissipation when all inputs are CMOS level and in static state.
•
Operation timing characteristics (Ta = – 20 to + 70°C, V
Parameter
SK clock frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E / W
CC
= 1.8 to 4.0 V)
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
250
—
—
—
—
—
—
—
2
2
2
400
25
Unit
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
ms
Min.
—
1
1
1
200
400
0
400
—
—
—
—
—
3
Memory ICs
BR93LL46F / BR93LL46FV
•
Timing chart
CS
t
CSS
SK
t
DIS
DI
t
PD0
DO (READ)
t
DF
DO (WRITE)
STATUS VALID
t
PD1
t
DF
t
DIH
t
SKH
t
SKL
t
CSH
Fig. 1 Synchronous data timing
(1) Data is acquired from DI in synchronization with the
SK rise.
(2) During a reading operation, data is output from DO
in synchronization with the SK rise.
(3) During a writing operation, a Status Valid (READY
or BUSY) is valid from the time CS is HIGH until time
t
CS
after CS falls following the input of a write command
and before the output of the next command start bit.
Also, DO must be in a HIGH-Z state when CS is LOW.
(4) After the completion of each mode, make sure that
CS is set to LOW, to reset the internal circuit, before
changing modes.
•
Circuit operation
(1) Command mode
Command
Read (READ)
Write enabled (WEN)
W
Write (WRITE)
Write disabled (WDS)
(
∗
2)
(
∗
1)
Start
bit
1
1
1
1
Operating
code
10
00
01
00
Address
A5 ~ A0
11XXXX
A5 ~ A0
00XXXX
Data
—
—
D15 ~ D0
—
X: Either V
IH
or V
IL
∗
About the start bit
With these ICs, commands are not recognized or acted
upon until the start bit is received. The start bit is taken
as the first “1” that is received after the CS pin rises.
(∗1) After setting of the read command and input of the
SK clock, data corresponding to the specified address
is output, with data corresponding to upper addresses
then output in sequence. (Auto increment function)
(∗2) When the write command is executed, all data in
the selected memory cell is erased automatically, and
the input data is written to the cell.
4
Memory ICs
(2) Reading
CS
SK
DI
DO
BR93LL46F / BR93LL46FV
( 1)
1
1
∗
2
1
0
4
A5
A4
A1
9
A0
0
10
25
26
High-Z
D15 D14
D1
( 2)
D0 D15 D14
∗
Fig.2 Read cycle timing (READ)
When the read command is acknowledged, the data
(16 bits) for the input address is output serially. The
data is synchronized with the SK rise during A0 acqui-
sition and a “0” (dummy bit) is output. All further data is
output in synchronization with the SK pulse rises.
(
∗1)
Start bit
The start bit is taken as the first “1” that is received
after the CS pin rises. Also, if “0” is input several times
followed by “1”, the “1” is recognized as a start bit, and
subsequent operation commences.
This applies also to the following commands.
(
∗2)
Address auto increment function
These ICs are equipped with an address auto incre-
ment function which is effective only during reading
operations. With this function, if the SK clock is input
following execution of one of the above reading com-
mands, data is read from upper addresses in succes-
sion. CS is held in HIGH state during automatic incre-
menting.
(3) Write enable
CS
SK
DI
DO
1
0
0
1
1
High-Z
These ICs are set to the write disabled state by the
internal reset circuit when the power is turned on.
Therefore, before performing a write command, the
write enable command must be executed. When this
command is executed, it remains valid until a write dis-
able command is issued or the power supply is cut off.
However, read commands can be used in either the
write enable or write disable state.
Fig.3 Cycle timing that allows overwriting
5
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