Memory ICs
2,048-Bit Serial Electrically Erasable PROM
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
•
Features CMOS technology
• Low power
• 128
×
16 bit configuration
• 2.7V to 5.5V operation
• Low power dissipation
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V
• Auto increment for efficient data bump
• Automatic erase-before-write
• Hardware and software write protection
– Default to write-disabled state at power up
– Software instructions for write-enable / disable
– Vcc lock out inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
• Device status signal during write cycle
• TTL compatible Input / Output
• 100,000 ERASE / write cycles
• 10 years Data Retention
•
Pin assignments
CS 1
SK 2
DI
3
8 V
CC
7 N.C.
N.C. 1
V
CC
2
CS
SK
3
4
8
7
6
5
N.C.
GND
DO
DI
BR93LC56 /
BR93LC56RF
6 N.C.
5 GND
BR93LC56F /
BR93LC56FV
DO 4
•
Pin descriptions
Pin
name
CS
SK
DI
DO
GND
N.C.
N.C.
V
CC
Chip select input
Serial clock input
Start bit, operating code, address, and serial
data input
Serial data output, READY / BUSY internal
status display output
Ground
Not connected
Not connected
Power supply
Function
•
Overview is CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically.
The BR93LC56
Each is configured of 128 words
×
16 bits (2,048 bits), and each word can be accessed individually and data read
from it and written to it.
Operation control is performed using five types of commands. The commands, addresses, and data are input
through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or
BUSY) can be output from the DO pin.
The only difference between the BR93LC56 / F / RF / FV is the write disable voltage and its accompanying write
enable voltage. All other functions and characteristics are the same.
1
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
•
Block diagram
Power supply
CS
Command decode
Control
Clock generation
Write
voltage detector
High voltage
generator
SK
disable
Address
Command
7bit
buffer
Address
decoder
7bit
2,048-bit
DI
register
Data
16bit
register
amplifier
R/W
16bit
EEPROM array
DO
Dummy bit
•
Absolute maximum ratings (Ta = 25°C)
Parameter
Applied voltage
BR93LC56
Power
BR93LC56F / RF
dissipation
BR93LC56FV
Storage temperature
Operating temperature
Terminal voltage
Symbol
V
CC
Limits
– 0.3 ~ + 6.5
500
∗
1
Pd
350
∗
2
300
∗
3
Tstg
Topr
—
– 65 ~ + 125
– 40 ~ + 85
– 0.3 ~ V
CC
+ 0.3
°C
°C
V
mW
Unit
V
∗
1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
∗
2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.
∗
3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
•
Recommended operating conditions (Ta = 25°C)
Parameter
Power supply
voltage
Input voltage
Writing
Reading
V
IN
Symbol
V
CC
Min.
2.7
2.0
0
Typ.
—
—
—
Max.
5.5
5.5
V
CC
Unit
V
V
V
2
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
CC
•
Electrical characteristics (unless otherwise noted, Ta = – 40 to + 85°C, V
Parameter
Input low level voltage
Input high level voltage
Output low level voltage 1
Output high level voltage 1
Output low level voltage 2
Output high level voltage 2
Input leakage current
Output leakage current
Operating current
dissipation 1
Operating current
dissipation 2
Standby current
I
CC2
I
SB
—
—
0.7
1.0
1.5
5
mA
µA
Symbol
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
I
LI
I
LO
I
CC1
Min.
– 0.3
2.0
—
2.4
—
V
CC
– 0.4
– 1.0
– 1.0
—
Typ.
—
—
—
—
—
—
—
—
1.5
Max.
0.8
V
CC
+ 0.3
0.4
—
0.2
—
1.0
1.0
3
Unit
V
V
V
V
V
V
µA
µA
mA
= 5V ± 10%)
Conditions
—
—
I
OL
= 2.1mA
I
OH
= – 0.4mA
I
OL
= 10µA
I
OH
= – 10µA
V
IN
= 0V ~ V
CC
V
OUT
= 0V ~ V
CC
, CS = GND
V
IN
= V
IH
/ V
IL
, DO = OPEN
f = 1MHz, WRITE
V
IN
= V
IH
/ V
IL
, DO = OPEN
f = 1MHz, READ
CS = SK = DI = GND, DO = OPEN
(unless otherwise noted, Ta = – 40 to + 85°C, V
CC
= 3V ± 10%)
Parameter
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Operating current
dissipation 1
Operating current
dissipation 2
Standby current
I
SB
—
0.4
3
µA
I
CC2
—
0.2
1
mA
Symbol
V
IL
V
IH
V
OL
V
OH
I
LI
I
LO
I
CC1
Min.
– 0.3
0.7
×
V
CC
—
V
CC
– 0.4
– 1.0
– 1.0
—
Typ.
—
—
—
—
—
—
0.5
Max.
0.15
×
V
CC
V
CC
+ 0.3
0.2
—
1.0
1.0
2
Unit
V
V
V
V
µA
µA
mA
I
OL
= 10µA
I
OH
= – 10µA
V
IN
= 0V ~ V
CC
V
OUT
= 0V ~ V
CC
, CS = GND
V
IN
= V
IH
/ V
IL
, DO = OPEN,
f = 250kHz, WRITE
V
IN
= V
IH
/ V
IL
, DO = OPEN,
f = 250kHz, READ
CS = SK = DI = GND, DO = OPEN
CC
Conditions
—
—
•
Electrical characteristics (unless otherwise noted, Ta = – 40 to + 85°C, V
Parameter
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Operating current
dissipation 2
Standby current
I
CC2
I
SB
—
—
0.2
0.4
1
3
mA
µA
Symbol
V
IL
V
IH
V
OL
V
OH
I
LI
I
LO
Min.
– 0.3
0.7
×
V
CC
—
V
CC
– 0.4
– 1.0
– 1.0
Typ.
—
—
—
—
—
—
Max.
0.15
×
V
CC
V
CC
+ 0.3
0.2
—
1.0
1.0
Unit
V
V
V
V
µA
µA
= 2.0V ± 10%)
Conditions
—
—
I
OL
= 10µA
I
OH
= – 10µA
V
IN
= 0V ~ V
CC
V
OUT
= 0V ~ V
CC
, CS = 0V
V
IN
= V
IH
/ V
IL
, DO = OPEN
f = 200kHz, READ
CS = SK = DI = 0V, DO = OPEN
3
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
Command
Start Operating
code
bit
Address
•
Circuit operation
(1) Command mode
Data
With these ICs, commands are not rec-
1
10
—
0A6 ~ A0
Read (READ)
∗
1
ognized or acted upon until the start bit
1
00
—
11XXXXXX
Write enabled (WEN)
is received. The start bit is taken as the
1
01
0A6 ~ A0 D15 ~ D0
Write (WRITE)
∗
2
first “1” that is received after the CS pin
1
00
01XXXXXX D15 ~ D0
Write all addresses (WRAL)
∗
2
rises.
∗1
After setting of the read command
1
00
—
00XXXXXX
Write disabled (WDS)
and input of the SK clock, data corre-
1
11
—
0A6 ~ A0
Erase (ERASE)
∗
3
sponding to the specified address is
1
00
—
10XXXXXX
Chip erase (ERAL)
∗
3
output, with data corresponding to up-
X: Either V
IH
or V
IL
per addresses then output in se-
quence. (Auto increment function)
∗2
When the write or write all addresses command is executed, all data in the selected memory cell is erased auto-
matically, and the input data is written to the cell.
∗3
These modes are optional modes. Please contact Rohm for information on operation timing.
(2) Operation timing characteristics
(unless otherwise noted, Ta = – 40 to + 85°C, V
CC
= 5V ± 10%)
Parameter
SK clock frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E / W
Min.
—
450
450
450
50
100
0
100
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
1
—
—
—
—
—
—
—
500
500
500
100
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
4
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
For low voltage operation (unless otherwise noted, Ta = – 40 to + 85°C, V
CC
= 3V ± 10%)
Parameter
SK clock frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
E / W
Min.
—
1
1
1
200
400
0
400
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
250
—
—
—
—
—
—
—
2
2
2
400
25
Unit
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
ms
When reading at low voltage (unless otherwise noted, Ta = – 40 to + 85°C, V
CC
= 2.0V)
Parameter
SK clock frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output High impedance
Not designed for radioactive rays.
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
DF
Min.
—
2
2
2
400
800
0
800
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
200
—
—
—
—
—
—
—
4
4
800
Unit
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
ns
5
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