88F619x
Hardware Specifications
Document Conventions
Note:
Provides related information or information of special importance.
Caution:
Indicates potential damage to hardware or software, or loss of data.
Warning:
Indicates a risk of personal injury.
Document Status
Doc Status: Preliminary
Technical Publication: 0.xx
For more information, visit our website at:
www.marvell.com
Disclaimer
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose,
without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any
kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any
particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.
Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use
Marvell products in these types of equipment or applications.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control
Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are
controlled for national security reasons by the EAR; and,
3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant,
not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons
by the EAR, or is subject to controls under the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any
such information.
Copyright © 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas,
Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell.
Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All
other trademarks are the property of their respective owners.
Doc. No. MV-S104987-U0 Rev. F
Page 2
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary
Features
FEATURES
88F6190
– Incorporates a single GbE port and a single
SATA port. CPU speed is up to 600 MHz.
88F6192
– Incorporates two GbE ports and two SATA
ports. CPU speed is up to 800 MHz. It also supports a
Sony/Philips Digital Interconnect Format / Integrated
Interchip Sound (S/PDIF / I
2
S) Audio interface, a TDM
SLIC/SLAC Codec interface, and an MPEG Transport
Stream (TS) interface.
The 88F6190 and 88F6192 controllers include:
•
High-performance CPU core, running at up to
600 MHz in the 88F6190 or 800 MHz in the
88F6192, with integrated, four-way, set-associative
L1 16-KB I-cache/16-KB D-cache and unified,
256-KB, four-way, set-associative L2 cache
•
High-bandwidth dual-port DDR2 memory interface
(16-bit DDR2 SDRAM @ up to 400 MHz data rate)
•
PCI Express (x1) port with integrated PHY
•
Gigabit Ethernet (10/100/1000 Mbps) MAC(s)
•
USB 2.0 port with integrated PHY
•
SATA 2.0 port(s) with integrated 3 Gbps SATA II PHY
•
Security Cryptographic engine
S/PDIF / I
2
S Audio in/out interface (88F6192 only)
SD/SDIO/MMC interface
TDM SLIC/SLAC Codec interface (88F6192 only)
Two XOR engines, each containing two XOR/DMA
channels (a total of four XOR/DMA channels)
•
MPEG Transport Stream (TS) interface
(88F6192 only)
•
SPI port with SPI flash boot support
•
8-bit NAND flash interface with boot support
•
Two 16550 compatible UART interfaces
•
TWSI port
•
36 multi-purpose pins
•
Internal Real Time Clock (RTC)
•
Interrupt controller
•
Timers
•
128-bit eFuse (one-time programmable memory)
Sheeva
™
CPU core
•
88F6190 – Up to 600 MHz
•
88F6192 – Up to 800 MHz
•
32-bit and 16-bit RISC architecture
•
Compliant with v5TE architecture, as published in
the
ARM Architect Reference Manual,
Second
Edition
•
Includes MMU to support virtual memory features
•
256-KB, four-way, set-associative L2 unified cache
•
16-KB, four-way, set-associative I-cache
•
16-KB, four-way, set-associative D-cache
•
64-bit internal data bus
•
Branch Prediction unit
•
Supports JTAG/ARM ICE
•
Supports both Big and Little Endian modes
DDR2 SDRAM controller
•
16-bit interface
•
Up to 200 MHz clock frequency (400 MHz data rate)
•
DDR SDRAM with a clock ratio of 1:N and 2:N
between the DDR SDRAM and the CPU core,
respectively
•
SSTL 1.8V I/Os
•
Auto calibration of I/Os output impedance
•
Supports two DRAM chip selects
•
Supports all DDR devices densities up to1 Gb
•
Supports up to16 open pages (page per bank)
•
Up to 512 MB total address space
•
Supports on-board DDR designs (no DIMM support)
•
Supports 2T mode, to enable high-frequency
operation under heavy load configuration
•
Supports DRAM bank interleaving
•
Supports up to a 128-byte burst per single memory
access
PCI Express interface (x1)
•
PCI Express Base 1.1 compatible
•
Integrated low-power SERDES PHY, based on
proven Marvell
®
SERDES technology
•
Serves as a Root Complex or an Endpoint port
•
x1 link width
•
2.5 Gbps data rate
•
Lane polarity reversal support
•
Maximum payload size of 128 bytes
•
Single Virtual Channel (VC-0)
•
Replay buffer support
•
Extended PCI Express configuration space
•
Advanced Error Reporting (AER) support
•
Power management: L0s and software L1 support
•
Interrupt emulation message support
•
Error message support
PCI Express master specific features
•
Single outstanding read transaction
•
Maximum read request of up to 128 bytes
•
Maximum write request of up to 128 bytes
•
Up to four outstanding read transactions in
Endpoint mode
PCI Express target specific features
•
Supports up to eight read request transactions
•
Maximum read request size of 4 KB
•
Maximum write request of 128 bytes
•
•
•
•
Copyright © 2008 Marvell
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F
Page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
