The outputs of the UT7R995/C can be configured to run at fre-
quencies ranging from 6 MHz to 200 MHz. Each output bank
has the ability to run at separate frequencies and with various
phase skews. Furthermore, numerous clock division and multi-
plication options exist.
The following discussion and list of tables will summarize the
available configuration options for the UT7R995/C. Tables 1
through 12, are relevant to the following configuration discus-
sions.
Table 1. Feedback Divider Settings (N-factor)
Table 2. Reference Divider Settings (R-Factor)
Table 3. Output Divider Settings - Bank 3 (K-factor)
Table 4. Output Divider Settings - Bank 4 (M-Factor)
Table 5. Frequency Divider Summary
Table 6. Calculating Output Frequency Settings
Table 7. Frequency Range Select
Table 8. Multiplication Factor (MF) Calculation
Table 9. Signal Propagation Delays in Various Media
Table 10: Output Skew Settings
Table 11. PE/HD Settings
Table 12. Power Supply Constraints
1.1 Divider Configuration Settings:
The feedback input divider is controlled by the 3-level DS[1:0]
pins as indicated in Table 1 and the reference input divider is
controlled by the 3-level PD/DIV pin as indicated in Table 2.
Although the Reference divider will continue to operate when
the UT7R995/C is in the standard TEST mode of operation, the
Feedback Divider will not be available.
Table 1: Feedback Divider Settings (N-factor)
DS[1:0]
LL
LM
LH
ML
MM
MH
HL
HM
HH
Table 2: Reference Divider Settings (R-factor)
PD/DIV
LOW
1
MID
HIGH
Operating Mode
Powered Down
Normal Operation
Normal Operation
Reference Input
Divider -
(R)
Not Applicable
2
1
Notes:
1. When PD/DIV = LOW, the device enters power-down mode.
In addition to the reference and feedback dividers, the
UT7R995/C includes output dividers on Bank 3 and Bank 4,
which are controlled by 3F[1:0] and 4F[1:0] as indicated in Ta-
bles 3 and 4, respectively.
Table 3: Output Divider Settings - Bank 3 (K-factor)
3F(1:0)
LL
HH
Other
1
Bank 3 Output Divider -
(K)
2
4
1
Notes:
1. These states are used to program the phase of the respective banks. Please see
Equation 1 along with Tables 8 and 10.
Table 4: Output Divider Settings - Bank 4 (M-factor)
4F[1:0]
LL
Other
1
Bank 4 Output Divider
(M)
2
1
Feedback Input
Divider -
(N)
2
3
4
5
1
6
8
10
12
Permitted Output
Divider (K or M)
Connected to FB
1, 2 or 4
1, 2 or 4
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
Notes:
1. These states are used to program the phase of the respective banks. Please see
Equation 1 along with Tables 8 and 10.
Each of the four divider options and their respective settings are
summarized in Table 5. By applying the divider options in Ta-
ble 5 to the calculations shown in Table 6, the user determines
the proper clock frequency for every output bank.
Table 5: Frequency Divider Summary
Division
Factors
N
Available Divider Settings
1, 2, 3, 4, 5, 6, 8, 10, 12
1, 2
1, 2, 4
1, 2
1
R
1
K
M
3
Table 6: Calculating Output Frequency Settings
Configuration
Clock Output
Connected to FB
1Qn or 2Qn
3Qn
4Qn
Output Frequency
1Q[1:0]
1
and
2Q[1:0]
1
(N/R) * f
XTAL
(N/R) * K * f
XTAL
(N/R) * M * f
XTAL
(N/R) * (1/K) * f
XTAL
(N/R) * f
XTAL
(N/R) * (M/K) * f
XTAL
(N/R) * (1/M) * f
XTAL
(N/R) * (K/M) * f
XTAL
(N/R) * f
XTAL
3Q[1:0]
4Q[1:0]
Notes:
1. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the nominal VCO operating frequency (f
NOM
)
at a given reference frequency (f
XTAL
) and the divider and feedback configuration. The user must select a configuration and a reference frequency that will generate
a VCO frequency that is within the range specified by FS pin. Please see Table 7.
1.2 Frequency Range and Skew Selection:
The PLL in the UT7R995/C operates within three nominal fre-
quency ranges. Depending upon the desired PLL operating fre-
quency, the user must define the state of the ternary FS control
pin. Table 7 defines the required FS selections based upon the
nominal PLL operating frequency ranges. Because the clock
outputs on Bank 1 and Bank 2 do not include a divider option,
they will always reflect the current frequency of the PLL. Ref-
erence the first column of equations in Table 6 to calculate the
value of f
NOM
for any given feedback clock.
Table 7: Frequency Range Select
FS
L
M
H
After calculating the time unit (t
U
) based on the nominal PLL
frequency (f
NOM
) and multiplication factor (MF), the circuit
designer plans routing requirements of each clock output and its
respective destination receiver. With an understanding of signal
propagation delays through a conductive medium (see Table 9),
the designer specifies trace lengths which ensure a signal prop-
agation delay that is equal to one of the t
U
multiples show in Ta-
ble 10. For each output bank, the t
U
skew factors are selected
with the tri-level, bank-specific, nF[1:0] pins.
Table 8: MF Calculation
FS
L
M
H
MF
32
16
8
Nominal PLL Frequency Range
(f
NOM
)
24 to 50 MHz
48 to 100MHz
96 to 200 MHz
f
NOM
examples that result
in a t
U
of 1.0ns
31.25 MHz
62.5 MHz
125 MHz
Selectable output skew is in discrete increments of time unit
(t
U
). The value of t
U
is determined by the FS setting and the
PLL’s operating frequency (f
NOM
). Use the following equation
to calculate the time unit (t
U
):
Equation 1.
t
=
1
(f
NOM
* MF)
Table 9: Signal Propagation Delays in Various Media
Medium
Air (Radio Waves)
Coax. Cable (75% Velocity)
Coax. Cable (66% Velocity)
FR4 PCB, Outer Trace
FR4 PCB, Inner Trace
Alumina PCB, Inner Trace
Propagation
Dielectric
Delay (ps/inch) Constant
85
113
129
140 - 180
180
240 - 270
1.0
1.8
2.3
2.8 - 4.5
4.5
8 - 10
u
The f
NOM
term, which is calculated with the help of Table 6,
must be compatible with the nominal frequency range selected
by the FS signal as defined in Table 7. The multiplication factor
(MF), also determined by FS, is shown in Table 8. The
UT7R995/C output skew steps have a typical accuracy of +/-
15% of the calculated time unit (t
U
).
4
Table 10: Output Skew Settings
4
nF[1:0]
LL
1, 2
LM
LH
ML
MM
MH
HL
HM
HH
2
Skew
1Q[1:0], 2Q[1:0]
-4t
U
-3t
U
-2t
U
-1t
U
Zero Skew
+1t
U
+2t
U
+3t
U
+4t
U
Skew
3Q[1:0]
Divide by 2
-6t
U
-4t
U
-2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Divide by 4
Skew
4Q[1:0]
Divide by 2
-6t
U
-4t
U
-2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Inverted
3
A graphical summary of Table 10 is shown in Figure 3. The
drawing assumes that the FB input is driven by a clock output
programmed with zero skew. Depending upon the state of the
nF[1:0] pins the respective clocks will be skewed, divided, or
inverted relative to the fedback output as shown in Figure 3.
1.3 Output Drive, Synchronization, and Power Supplies:
The UT7R995/C employs flexible output buffers providing the
user with selectable drive strengths, independent power sup-
plies, and synchronization to either edge of the reference input.
Using the 3-level PE/HD pin, the user selects the reference edge
synchronization and the output drive strength for all clock out-
puts. The options for edge synchronization and output drive
strength selected by the PE/HD pin are listed in Table 11.
Table 11: PE/HD Settings
PE/HD
Synchronization
Output Drive
Strength
1
L
M
H
Negative
Positive
Positive
Low Drive
High Drive
Low Drive
Notes:
1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH.
2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversion-
options function as defined in Table 9.
3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these out-
puts HIGH when PE/HD = HIGH or MID, sOE disables them LOW when
PE/HD = LOW.
4. Skew accuracy is within +/- 15% of n*t
U
where "n" is the selected number
of skew steps. Supplied as a design limit, but not tested or guaranteed.
Notes:
1. Please refer to "DC Parameters" section for I
OH
/I
OL
specifications.
XTAL1 Input
FB Input
1F[1:0]
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
2F[1:0]
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
3F[1:0]
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
(N/A)
4F[1:0]
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL
HH
-6t
U
-4t
U
-3t
U
-2t
U
-1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERTED
Figure 3. Typical Outputs with FB Connected to a Zero-Skewed Output
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
