M
25AA640/25LC640/25C640
64K SPI
™
Bus Serial EEPROM
PACKAGE TYPES
Temp
Ranges
C,I
C,I
C,I,E
CS
SO
WP
V
SS
PDIP/SOIC
1
25xx640
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
Max Clock
Frequency
1 MHz
2 MHz
3 MHz
DEVICE SELECTION TABLE
Part
Number
25AA640
25LC640
25C640
V
CC
Range
1.8-5.5V
2.5-5.5V
4.5-5.5V
FEATURES
• Low power CMOS technology
- Write current: 3 mA typical
- Read current: 500
µ
A typical
- Standby current: 500 nA typical
• 8192 x 8 bit organization
• 32 byte page
• Write cycle time: 5ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection
- Protect none, 1/4, 1/2, or all of array
• Built-in write protection
- Power on/off data protection circuitry
- Write enable latch
- Write protect pin
• Sequential read
• High reliability
- Endurance: 1M cycles (guaranteed)
- Data retention: > 200 years
- ESD protection: > 4000 V
• 8-pin PDIP, SOIC, and TSSOP packages
• Temperature ranges supported:
- Commercial: (C)
0
°
C to +70
°
C
- Industrial: (I)
-40
°
C to +85
°
C
- Automotive: (E) (25C640)
-40
°
C to +125
°
C
TSSOP
HOLD
V
CC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
V
SS
WP
25xx640
BLOCK DIAGRAM
Status
Register
HV Generator
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Dec
Page Latches
Array
DESCRIPTION
The Microchip Technology Inc. 25AA640/25LC640/
25C640 (25xx640
*
) is a 64K bit serial Electrically Eras-
able PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a chip select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
SI
SO
CS
SCK
HOLD
WP
V
CC
V
SS
Sense Amp.
R/W Control
Y Decoder
*25xx640 is used in this document as a generic part number for the 25AA640/25LC640/25C640 devices.
SPI is a trademark of Motorola.
©
1997 Microchip Technology Inc.
Preliminary
DS21223A-page 1
25AA640/25LC640/25C640
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
FIGURE 1-1:
AC TEST CIRCUIT
V
CC
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V
Storage temperature ....................................... -65˚C to 150˚C
Ambient temperature under bias..................... -65˚C to 125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins.................................................4kV
*Notice:
Stresses above those listed under ‘Maximum ratings’ may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability
2.25 K
SO
1.8 K
100 pF
1.2
AC Test Conditions
AC Waveform:
TABLE 1-1:
Name
CS
SO
SI
SCK
WP
V
SS
V
CC
HOLD
PIN FUNCTION TABLE
Function
Chip Select Input
Serial Data Output
Serial Data Input
Serial Clock Input
Write Protect Pin
Ground
Supply Voltage
Hold Input
V
LO
= 0.2V
V
H I
= V
CC
- 0.2V
V
H I
= 4.0V
Input
Output
Note 1:
For V
CC
≤
4.0V
2:
For V
CC
> 4.0V
(Note 1)
(Note 2)
0.5 V
CC
0.5 V
CC
Timing Measurement Reference Level
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C):
Industrial (I):
Automotive (E):
Tamb = 0
°
C to +70
°
C
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to +125
°
C
V
CC
= 1.8V to 5.5V
V
CC
= 1.8V to 5.5V
V
CC
= 4.5V to 5.5V (25C640 only)
All parameters apply over the
specified operating ranges
unless otherwise noted.
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Internal Capacitance
(all inputs and outputs)
Symbol
V
IH
1
V
IH
2
V
IL
1
V
IL
2
V
OL
V
OL
V
OH
I
LI
I
LO
C
INT
I
CC
Read
Min
2.0
0.7 V
CC
-0.3
-0.3
—
—
V
CC
-0.5
-10
-10
—
—
—
—
—
—
—
Max
V
CC
+1
V
CC
+1
0.8
0.3 V
CC
0.4
0.2
—
10
10
7
1
500
5
3
5
1
Units
V
V
V
V
V
V
V
µ
A
µ
A
pF
mA
µ
A
mA
mA
µ
A
µ
A
Test Conditions
V
CC
≥
2.7V (Note)
V
CC
< 2.7V (Note)
V
CC
≥
2.7V (Note)
V
CC
< 2.7V (Note)
I
OL
= 2.1 mA
I
OL
= 1.0 mA, V
CC
< 2.5V
I
OH
=-400
µ
A
CS = V
CC
, V
IN
= V
SS TO
V
CC
CS = V
CC
, V
OUT
= V
SS TO
V
CC
T
AMB
= 25˚C, CLK = 1.0 MHz,
V
CC
= 5.0V (Note)
V
CC
= 5.5V; F
CLK
=3.0 MHz; SO = Open
V
CC
= 2.5V; F
CLK
=2.0 MHz; SO = Open
V
CC
= 5.5V
V
CC
= 2.5V
CS = Vcc = 5.5V, Inputs tied to V
CC
or V
SS
CS = Vcc = 2.5V, Inputs tied to V
CC
or V
SS
Operating Current
I
CC
Write
I
CCS
Standby Current
Note:
This parameter is periodically sampled and not 100% tested.
DS21223A-page 2
Preliminary
©
1997 Microchip Technology Inc.
25AA640/25LC640/25C640
2.0
2.1
PIN DESCRIPTIONS
Chip Select (CS)
2.5
Write Protect (WP)
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already initi-
ated or in progress will be completed, regardless of the
CS input signal. If CS is brought high during a program
cycle, the device will go in standby mode as soon as
the programming cycle is complete. As soon as the
device is deselected, SO goes to the high impedance
state, allowing multiple parts to share the same SPI
bus. A low to high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a high to low transition on CS is required prior to
any sequence being initiated.
This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP is low and WPEN is
high, writing to the non-volatile bits in the status regis-
ter is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
non-volatile bits in the status register operate normally.
If the WPEN bit is set, WP low during a status register
write sequence will disable writing to the status regis-
ter. If an internal write cycle has already begun, WP
going low will have no effect on the write.
The WP pin function is blocked when the WPEN bit in
the status register is low. This allows the user to install
the 25AA640/25LC640/25C640 in a system with WP
pin grounded and still be able to write to the status reg-
ister. The WP pin functions will be enabled when the
WPEN bit is set high.
2.2
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.6
Hold (HOLD)
2.3
Serial Output (SO)
The SO pin is used to transfer data out of the 25xx640.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25xx640. Instructions,
addresses, or data present on the SI pin are latched
on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock
input.
The HOLD pin is used to suspend transmission to the
25xx640 while in the middle of a serial sequence with-
out having to re-transmit the entire sequence over at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication with-
out resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25xx640 must remain selected dur-
ing this sequence. The SI, SCK, and SO pins are in a
high impedance state during the time the part is
paused and transitions on these pins will be ignored.
To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
©
1997 Microchip Technology Inc.
Preliminary
DS21223A-page 5
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