PL123-05N/-09N
Low Skew Fanout Buffer
FEATURES
Output fanout buffer for DC to 134MHz
Output Options:
o
1:5 output fanout with
PL123-05
o
1:9 output fanout with
PL123-09
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
Low Additive Phase Jitter of 60fs RMS
2.5V to 3.3V, ±10% operation
1.8V ±10% operation up to 67MHz
Operating temperature range from -40°C to 85°C
Available in 16-Pin SOP (PL123-09) and 8-Pin
SOP (PL123-05). Both are GREEN/RoHS packag-
es.
DESCRIPTION
The PL123-05N and PL123-09N are a low-cost
fanout buffers for distributing high-speed clocks with
low output to output skew and preserving low noise
properties. The fanout buffers accept an input from
DC to 134MHz and provide 5 or 9 outputs of the same
frequency. A typical PL123-09N application for driving
SDRAM in PC systems would use eight outputs to
drive two DIMMs, or four SO-DIMMs, with the re-
maining output used for driving an external fee d-
back to a PLL. A typical PL123-05N application is
to fanout a low noise CMOS clock oscillat or to 5
low noise CMOS clocks.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM AND PACKAGE PINOUT
CLK1
PL123-05N
CLK2
REF
CLK3
CLK4
CLK5
CLK1
CLK2
CLK3
CLK4
REF
CLK5
CLK6
CLK7
CLK8
CLK9
REF
CLK1
CLK2
GND
1
2
3
4
8
7
6
5
CLK5
CLK4
VDD
CLK3
SOP-8L
REF
CLK1
CLK2
VDD
GND
CLK3
CLK4
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK9
CLK8
CLK7
VDD
GND
CLK6
CLK5
GND
SOP-16L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/15/12
PL123-09N
Page 1
PL123-05N/-09N
Low Skew Fanout Buffer
PIN DESCRIPTIONS
Name
REF
CLK1
CLK2
VDD
GND
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
PL123-09N
SOP-16L
1
2
3
4, 8, 13
5, 9, 12
6
7
10
11
14
15
16
PL123-05N
SOP-8L
1
2
3
6
4
5
7
8
-
-
-
-
Type
I
O
O
P
P
O
O
O
O
O
O
O
Description
Input reference frequency.
Buffered clock output
Buffered clock output
VDD connection
GND connection
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a pe rformance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bounc ing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1
F
for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
( Typical buffer impedance 20 ohm)
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
To CMOS Input
50 ohm line
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/15/12 Page 2
PL123-05N/-09N
Low Skew Fanout Buffer
ABSOLUTE M AXIM UM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ............................ V
SS
– 0.5V to 4.6V
Storage Temperature ..........................–65°C to 150°C
Junction Temperature………………………….. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)…………..> 2000V
OPERATING CONDITIONS
Parameter
V
DD
T
A
Description
Supply Voltage
Commercial Operating Temperature (ambient temperature)
Industrial Operating Temperature (ambient te mperature)
Load Capacitance, below 100 MHz, V
DD
> 2.25V
C
L
C
IN
REF, CLK[1:9]
t
PU
Load Capacitance, above 100 MHz , V
DD
> 2.25V
Load Capacitance, below 67MHz, 1.62V < V
DD
< 2.25V
Input Capacitance
Operating Frequency, Input=Output, V
DD
> 2.25V
Operating Frequency, Input=Output, 1.62V < V
DD
< 2.25V
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
Min.
1.62
0
-40
―
―
―
―
DC
DC
0.05
Max.
3.63
70
85
30
10
15
7
134
67
50
Unit
V
C
C
pF
pF
pF
pF
MHz
MHz
ms
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/15/12 Page 3
PL123-05N/-09N
Low Skew Fanout Buffer
ELECTRICAL CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
[1]
Input HIGH Voltage
[1]
Input LOW Current
Input HIGH Current
Output LOW Voltage
[2]
Output HIGH Voltage
[2]
Supply Current
Test Conditions
V
DD
> 2.25V
V
DD
> 2.25V
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA , V
DD
> 2.97V
I
OH
= –8 mA , V
DD
> 2.97V
66.67MHz with unloaded outputs
Min.
–
2.0
–
–
–
2.4
–
Max.
0.8
–
50
100
0.4
–
32
Unit
V
V
µA
µA
V
V
mA
SWITCHING CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
[3 ]
Parameter
Description
Duty Cycle
[2]
= t2 ÷ t1
Test Conditions
Measured at 1.4V, V
DD
=3.3V, Input=50%
Measured at V
DD
/2 , Input = 50%
0.8V
2.0V , V
DD
=3.3V , 30pF Load
t
3
t
4
Rise Time
[2]
Fall Time
[2]
10%
90% , V
DD
=2.5V , 15pF Load
10%
90% , V
DD
=1.8V , 15pF Load
2.0V
0.8V , V
DD
=3.3V , 30pF Load
90%
10% , V
DD
=2.5V , 15pF Load
90%
10% , V
DD
=1.8V , 15pF Load
t
5
t
6
Output to Output Skew
[2]
Propagation Delay, REF Rising
Edge to CLKX Rising Edge
[2]
All outputs equally loaded
Measured at V
DD
/2
Min.
40
40
–
–
–
–
–
–
–
1
Typ.
50
50
–
–
–
–
–
–
–
5
Max.
60
60
1.5
2.5
4.5
1.5
2.5
4.5
250
9.2
Unit
%
%
ns
ns
ns
ns
ns
ns
ps
ns
Notes:
1. REF input has a threshold voltage of V
DD
/2
2. Parameter is guaranteed by design and characterization. Not 100% tested in p roduction.
3. All parameters are specified with loaded outputs.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/15/12 Page 4
PL123-05N/-09N
Low Skew Fanout Buffer
NOISE CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
Parameter
Description
Additive Phase Jitter
Test Conditions
V
DD
=3.3V, Frequency=100MHz
Offset=12KHz ~ 20MHz
Min.
Typ.
60
Max.
Unit
fs
PL123-09N Additive Phase Jitter:
VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical.
REF Input
-60
-70
-80
-90
PL123-09N Output
Phase Noise (dBc/Hz)
-100
-110
-120
-130
-140
-150
-160
10
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
2
2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/15/12 Page 5
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