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AN-4163 — Shielded Gate PowerTrench®
MOSFET Datasheet Explanation
Introduction
A MOSFET datasheet contains important technical
information for power system designers to choose proper
MOSFETs for specific applications. This application note
explains the electrical parameters and graphs specified in
datasheets PowerTrench® MOSFETs. The shielded gate
PowerTrench is Fairchild’s advanced trench MOSFET
design technology that supports MOSFETs rated up to
300 V. In this application note, the 100 V N-channel
FDMS86101A datasheet is used for explanation.
Table 1. Drain-to-Source Breakdown Voltage
Parameters
Symbol Parameter Conditions Min. Typ. Unit
BV
DSS
Drain-to-
Source
Breakdown
Voltage
I
D
= 250 µA,
V
GS
= 0 V
100
V
BV
DSS
T
J
1.
Drain-to-Source Breakdown
Voltage, BV
DSS
2.
Breakdown I
D
= 250 µA,
Voltage
Referenced to
Temperature
25°C
Coefficient
71
mV/°
C
The breakdown voltage between the drain and the source
terminal, BV
DSS
, is measured at 250 µA drain current, I
D
,
with the gate shorted to the source, which turns off the
MOSFET, as shown in Figure 1. Table 1 provides the
minimum value of BV
DSS
at 25°C junction temperature, T
J
.
The level of the BV
DSS
is proportional to the increase of T
J
positively. For example, the breakdown voltage temperature
coefficient
of
FDMS86101A,
BV
DSS
T
J
Gate-to-Source Voltage, V
GS
The sustainable voltage between the gate and the source
terminal is limited to the maximum voltage, V
GS
. It has the
positive and negative 20 V, shown in Table 2, and any gate
drive voltage must be less than the maximum V
GS
.
Designers should check the datasheet value for reliable
operation since the V
GS
varies by MOSFET technology.
Table 2. Gate to Source Voltage Parameters
Symbol
V
GS
is
71 mV/°C
typically. If T
J
of FDMS86101A reaches 100°C, the BV
DSS
increases by 5.325 V (75°C x 71 mV/°C). For more reliable
operation, special caution should be taken to not exceed the
BV
DSS
; especially at an inductive load condition.
Parameter
Gate to Source Voltage
Ratings
±20
Unit
V
3.
Drain
Gate-to-Source Threshold
Voltage, V
GS(th)
Gate
Source
DUT
I
D
The gate-to-source threshold voltage, V
GS(th)
, is defined
as a minimum gate electrode bias to conduct the 250 µA
drain current, I
D
. It has the negative temperature
V
GS
(
th
)
T
J
coefficient,
so it is decreased as the junction
temperature, T
J
rises. For example, when T
J
of
FDMS86101A becomes 100°C, V
GS(th)
is reduced by
0.675 V (75°C x -9 mV/°C). Minimum, typical, and
maximum values are specified in Table 3.
Figure 1.
Drain-to-Source Breakdown Voltage Test Circuit
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 10/23/14
www.fairchildsemi.com
AN-4163
APPLICATION NOTE
Table 3. Gate-to-Source Threshold Voltage Parameters
Symbol
V
GS(th)
V
GS
(
th
)
T
J
Parameter
Gate-to-Source Threshold Voltage
Gate-to-Source Threshold Voltage
Temperature Coefficient
Test Conditions
V
GS
= V
DS
, I
D
=250 µA
I
D
= 250 µA, Referenced to 25°C
Min.
2.0
Typ.
3.1
-9
Max.
4.0
Unit
V
mV/°C
4.
Static Drain-to-Source On Resistance, R
DS(on)
a different amplitude of the V
GS
and the drain current, I
D
, at
a junction temperature, T
J
. There are two graphs pertaining
to the static on-resistance.
The static drain-to-source on-resistance, R
DS(on)
, is described
at various gate voltages, V
GS
which are greater than the gate-
to-source threshold voltage, V
GS(th)
, and different drain
current levels in Table 4 because the R
DS(on)
value changes at
Table 4. Static Drain-to-Source On Resistance Parameters
Symbol
R
DS(on)
Parameter
Static Drain-to-Source On Resistance
Conditions
V
GS
= 10 V, I
D
= 13 A
V
GS
= 6 V, I
D
= 9.5 A
V
GS
= 10 V, I
D
= 13 A, T
J
=125°C
Min. Typ. Max. Unit
6.3
8.0
10.3
8.0
13.5
13.1
mΩ
The normalized drain-to-source on resistance is a function
of I
D
at a given V
GS
, as shown in Figure 2. V
GS
plays an
important role in changing the on resistance value. When
the V
GS
is decreased from 10 V
GS
to 5 V
GS
at 60 A of I
D
, the
R
DS(on)
increases three times, which can be translated to
18.9 mΩ (3 times 6.3 mΩ) and the maximum I
D
is saturated
at around 60 A with 5 V
GS
due to the increased R
DS(on)
.
Figure 3 shows the normalized drain-to-source on resistance
according to T
J
. The R
DS(on)
has a positive temperature
coefficient; so at the 125°C junction temperature, the static
drain-to-source on resistance of FDMS86101A is increased
by 1.63 times compared to the 25°C value. Therefore, in the
case of parallel operation, the drain current can be well
balanced among MOSFETs because increasing on
resistance caused by increasing junction temperature
prevents the drain current from flowing through only one or
a few channels of MOSFETs and then parallel connected
MOSFETs share the total drain current.
Figure 3.
Normalized On Resistance vs. T
J
By using two graphs showing normalized drain-to-source on
resistance values, the R
DS(on)
graph of Figure 4 as the
function of the V
GS
at both given T
J
and I
D
provides typical
R
DS(on)
values. For example, if I
D
is 13 A and V
GS
is 5 V in
25°C junction temperature, the typical R
DS(on)
is 10 mΩ.
Figure 2.
Normalized On Resistance vs. Drain Current
and Gate Voltage
Figure 4.
2
On Resistance vs. Gate-to-Source Voltage
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© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 10/23/14
AN-4163
APPLICATION NOTE
5.
Operating and Storage Junction
Temperature Range, T
J
Figure 5.
Mounted PCB Information for Thermal
Resistance
The operating and storage junction temperature, T
J
indicates
the recommended temperature range in which a MOSFET
operates reliably under specified electrical values. Most of
standard MOSFETs have -55°C to +150°C temperature
range like Table 5.
Table 5. Operating and Storage Junction
Temperature Parameters
Symbol
T
J
Parameter
Operating and Storage
Junction Temperature Range
Ratings
-55 to +150
Unit
°C
With these thermal resistance values, the maximum P
D
a
MOSFET can sustain is calculated. For example, the
maximum P
D
of FDMS86101A mounted on the 1 inch
2
PCB
pad can be calculated with R
ΘJA
at 25°C ambient
temperature from Table 6.
P
D
(
T
A
)
½
T
J
T
A
150
℃
- 25℃
½
½
2.5
W
R
ΘJA
50℃
/W
6.
Power Dissipation, P
D
Table 7 describes the maximum allowable P
D
based on each
condition.
Table 7. Power Dissipation Parameters
Symbol
P
D
The power dissipation, P
D
, is the maximum allowable power
limit of a device. The two P
D
parameters are dependent on
specific temperature conditions: case temperature, T
C
, and
ambient temperature, T
A
. These parameters are calculated
with Equations (1) and (2), respectively:
T
T
C
P
D
(
T
C
)
½
J
R
ΘJC
(1)
(2)
Parameter
Power Dissipation, T
C
=25°C
Power Dissipation, T
A
=25°C
(Figure 5a)
Ratings
104
2.5
Unit
W
W
P
D
(
T
A
)
½
T
J
T
A
R
ΘJA
7.
Continuous Drain Current, I
D
Thermal resistance is the ability to transfer heat from device
to outside. Typically, two thermal resistances are provided
in the datasheet, as shown in Table 6: junction-to-case
thermal resistance, R
ΘJC
, and junction-to-ambient thermal
resistance, R
ΘJA
. R
ΘJA
is the sum of the junction-to-case
resistance, R
ΘJC
, and the case-to-ambient thermal resistance,
R
ΘCA
, where the case thermal reference is defined as the
solder mounting surface of the device package. R
ΘJC
is
guaranteed by design, while R
ΘJA
is determined by board
conditions such as a PCB material, a mounted pad area, and
layer number. Figure 5 shows the PCB information of the
large 1-inch
2
and minimum pad sizes when the junction-to-
ambient thermal resistance is measured.
Table 6. Thermal Resistance Parameters
Symbol
R
ΘJC
Two continuous drain currents are specified in the datasheet
based on the case temperature, T
C
, and the ambient
temperature, T
A
. They can be calculated with Equations (3)
and (4), respectively.
I
D
(
T
C
) ½
T
J
T
C
R
DS
(
ON
),
TJ
(
MAX
)
R
ΘJC
T
J
T
A
R
DS
(
ON
),
TJ
(
MAX
)
R
ΘJA
(3)
I
D
(
T
A
) ½
(4)
Parameter
Thermal Resistance, Junction-
to-Case
Thermal Resistance, Junction-
to-Ambient (Figure 5a)
Thermal Resistance, Junction-
to-Ambient (Figure 5b)
Ratings Unit
1.2
50
125
°C/W
The I
D
of FDMS86101A at T
C
=25°C can be computed with
RΘ
JC
and R
DS(on)
at the maximum T
J
of 150°C. As the R
DS(on)
is increased by the rise of T
J
, the R
DS(on)
at the maximum T
J
is calculated by multiplying the normalized factor at the
150°C junction temperature from Figure 3. Therefore, the
R
DS(on)
becomes 15.6 mΩ (8 mΩ x 1.95).
I
D
(
T
C
) ½
T
J
T
C
r
DS
(
ON
),
TJ
(
MAX
)
R
ΘJC
½
150℃
- 25℃
½ 81.7
A
8m
1.95 1.2℃
/W
°C/W
°C/W
R
ΘJA
It results in 81.7 A at the 25°C case temperature.
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 10/23/14
www.fairchildsemi.com
3
AN-4163
APPLICATION NOTE
9.
Forward Bias Safe Operating
Area, FBSOA
The forward bias safe operating area, FBSOA, is defined by
lines of the maximum allowable drain current, I
D
, under a
specific drain-to-source voltage, V
DS
, when a MOSFET is
turned on by a single pulse or a continuous voltage at the
T
A
=25°C and minimum PCB pad. The set of the curves
shows a DC line and five single pulse operating lines: 10 s,
1 s, 100 ms, 10 ms, and 1 ms in Figure 7.
b)
c)
Figure 6.
Maximum Continuous Drain Current vs.
Case Temperature
a)
d)
Another constraint is caused by the current capability of a
package. The I
D
of FDMS86101A at the 25°C case
temperature is limited by 60 A in Figure 6 due to its
package current capability. Table 8 describes the maximum
continuous drain current based on each condition.
Table 8. Continuous Drain Current Parameters
Symbol
Parameter
Continuous Drain Current,
T
C
=25°C
Continuous Drain Current,
T
A
=25°C (Figure 5 - a)
e)
Ratings
60
13
Unit
A
A
Figure 7.
Forward Bias Safe Operating Area
I
D
There are five limitations from the a) to the e) line:
a.
Limited by the static drain-to-source on resistance,
R
DS(on)
. For example, when the V
DS
is 0.01 V, the
I
D
of FDMS86101A is limited to 1.25 A due to
Ohm’s law. (Typical the R
DS(on)
of FDMS86101A
at 10 V
GS
is 8 mΩ, from Table 4.)
I
D
½
V
DS
0.01
V
½
½
1.25
A
r
DS(on)
8m
8.
Forward Transconductance, g
FS
The forward transconductance, g
FS
, is the gain of the
MOSFET expressed in Equation (5). It is the rate of change
of the drain current,
△I
D
, per a change of the gate-to-source
voltage variance,
△V
GS
, at a constant drain voltage, V
DS
. A
large transconductance is desirable to obtain a high current
capability with low gate voltage:
I
g
FS
½
DS
V
GS
VDS
(5)
b.
c.
d.
Limited by the maximum power dissipation, P
D
is
explained in Section 6.
Limited by the maximum drain current, I
D
is
explained in Section 7.
Limited by the thermal run away in the linear
region, Figure 8 shows the I
D
as the function of the
V
DS
at a given V
GS
. The on-state operation of a
MOSFET is divided into the ohmic region and the
linear region, defined by V
DS
= V
GS
– V
GS(th)
as the
boundary line. In the ohmic region, located to the
left of the boundary line (V
DS
< V
GS
– V
GS(th)
); the
I
D
is defined by Ohm’s law and increases linearly
with the incremental drain voltage. In the linear
region, to the right of the boundary line (V
DS
> V
GS
– V
GS(th)
); the I
D
differs by the V
GS
, not by V
DS
. For
example, when the V
DS
is 4 V and V
GS
is 4.5 V, the
FDMS86101A operates in the linear region and its
I
D
stays at around 17 A. To increase I
D
, a higher
V
GS
should be applied to the gate.
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The typical g
FS
value at the specific condition is listed in
Table 9.
Table 9. Forward Transconductance Parameter
Symbol
g
FS
Parameter
Conditions
Typ. Unit
53
S
Forward
V
GS
= 10 V,
Transconductance I
D
= 13 A
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 10/23/14
4
AN-4163
APPLICATION NOTE
Ohmic region
Linear region
ZTC point
Figure 8.
On-Region Characteristics
Figure 9.
Transfer Characteristics
Figure 9 expresses the I
D
as the function of the V
GS
at
given T
J
and 5 V of V
DS
. There is the crossover point
among the transconductance curves at each junction
temperature, which is called the Zero Temperature
Coefficient, ZTC. If V
GS
is above the ZTC point, a
MOSFET has a negative temperature coefficient. It
means if some cells within a MOSFET are getting
hotter than others, hotter cells have a higher R
DS(on)
and
their channels conduct less current, resulting in
stabilizing the heat across unit cells. However,
interestingly, a MOSFET has the positive temperature
coefficient when operating with V
GS
below the ZTC
point. The gate threshold voltage, V
GS(th)
, is reduced
with the increase of junction temperature, T
J
, and much
more drain current flows. In the case of operation in the
linear region with V
GS
less than the ZTC point, a local
hot spot within the MOSFET can occur and create non-
uniform heat on the die due to the positive temperature
coefficient. As a result, a thermal run away can occur in
the worst case. So the d) line of FBSOA is defined
based on real measurements.
e.
Limited by the drain-to-source breakdown voltage
explained in Section 1.
10. Transient Thermal Impedance,
Z
ΘJA
The steady-state thermal resistance values are not enough to
find a peak junction temperature in terms of pulse driven
applications. Figure 10 provides the normalized effective
transient thermal resistance, r(t), as a function of the
rectangular pulse duration at a given duty cycle. As the duty
cycle and the pulse duration increase, the transient thermal
impedance gets close to 1. This means the transient thermal
resistance approaches steady-state resistance. It calculate the
transient thermal impedance, Z
ΘJA
(t), which is used to
estimate the junction temperature, T
J
, resulting from a
transient power dissipation by using Equations (6) and (7):
Z
JA
(
t
)
½
R
JA
r
(
t
)
(6)
(7)
T
J
½
P
D
Z
JA
(
t
)
T
A
Figure 10. Junction-to-Ambient Transient Thermal Response Curve
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 10/23/14
www.fairchildsemi.com
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