GS71108ATP/J/SJ/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 140/120/95/80 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option:
–40°
to 85°C
• Package line up
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 32-pin TSOP Type II package
SJ: 300 mil, 32-pin SOJ package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
128K x 8
1Mb Asynchronous SRAM
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
V
DD
V
SS
DQ
3
DQ
4
WE
A
16
A
15
A
14
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7, 8, 10, 12 ns
3.3 V V
DD
Center V
DD
and V
SS
32
31
30
29
A
4
A5
A6
A
7
OE
DQ
8
DQ
7
V
SS
V
DD
DQ6
DQ
5
A
8
A
9
A
10
A
11
A
12
SOJ & TSOP-II 128K x 8-Pin Configuration
32-pin
400 mil SOJ
&
300 mil SOJ
&
400 mil TSOP II
28
27
26
25
24
23
22
21
20
19
18
17
Description
The GS71108A is a high speed CMOS Static RAM organized
as 131,072 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71108A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 300 mil and 400 mil
SOJ and 400 mil TSOP Type-II packages.
Packages J, TP, and SJ
Fine Pitch BGA 128K x 8-Bump Configuration
1
A
NC
DQ
1
DQ
2
V
SS
V
DD
DQ
3
DQ
4
NC
2
OE
NC
NC
NC
NC
NC
NC
A
10
3
A
2
A
1
A
0
NC
NC
A
14
A
15
A
16
4
A
6
A
5
A
4
A
3
NC
A
11
A
12
A
13
5
A
7
CE
NC
NC
NC
DQ
5
WE
A
9
6
NC
DQ
8
DQ
7
V
DD
V
SS
DQ
6
A
8
NC
Pin Descriptions
Symbol
A
0
–A
16
DQ
1
–DQ
8
CE
WE
OE
V
DD
V
SS
NC
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
B
C
D
E
F
G
H
Package U
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Rev: 1.04a 10/2002
1/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Block Diagram
A
0
Address
Input
Buffer
Row
Decoder
Memory Array
A
16
CE
WE
OE
Column
Decoder
Control
I/O Buffer
DQ
1
DQ
8
Truth Table
CE
H
L
L
L
Note: X: “H” or “L”
OE
X
L
X
H
WE
X
H
L
H
DQ
1
to DQ
8
Not Selected
Read
Write
High Z
V
DD
Current
ISB
1
, ISB
2
I
DD
Rev: 1.04a 10/2002
2/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
Symbol
V
DD
V
IN
V
OUT
PD
T
STG
Rating
–0.5
to +4.6
–0.5
to V
DD
+0.5
(≤ 4.6 V max.)
–0.5
to V
DD
+0.5
(≤ 4.6 V max.)
0.7
–55
to 150
Unit
V
V
V
W
o
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12
Input High Voltage
Input Low Voltage
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
Symbol
V
DD
V
IH
V
IL
T
Ac
T
A
I
Min
3.0
2.0
–0.3
0
–40
Typ
3.3
—
—
—
—
Max
3.6
V
DD
+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than
–2
V and not exceed 20 ns.
Rev: 1.04a 10/2002
3/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
C
IN
C
OUT
Test Condition
V
IN
= 0 V
V
OUT
= 0 V
Max
5
7
Unit
pF
pF
Notes:
1. Tested at T
A
= 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Input Leakage
Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Symbol
I
IL
I
LO
V
OH
V
OL
Test Conditions
V
IN
= 0 to V
DD
Output High Z
V
OUT
= 0 to V
DD
I
OH
=
–4
mA
I
LO
= +4 mA
Min
–1
uA
–1
uA
2.4
—
Max
1 uA
1 uA
—
0.4 V
Power Supply Currents
Parameter
Symbol
Test Conditions
CE
≤
V
IL
All other inputs
≥
V
IH
or
≤
V
IL
Min. cycle time
I
OUT
= 0 mA
CE
≥
V
IH
All other inputs
≥
V
IH
or
≤V
IL
Min. cycle time
CE
≥
V
DD
– 0.2 V
All other inputs
≥
V
DD
– 0.2 V or
≤
0.2 V
0 to 70°C
7 ns
8 ns
10 ns
12 ns
7 ns
–40 to 85°C
8 ns
10 ns
12 ns
Operating
Supply
Current
I
DD
140 mA 120 mA
95 mA
80 mA
145 mA
125 mA 100 mA
85 mA
Standby
Current
I
SB1
25 mA
20 mA
20 mA
15 mA
30 mA
25 mA
25 mA
20 mA
Standby
Current
I
SB2
2 mA
5 mA
Rev: 1.04a 10/2002
4/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
AC Test Conditions
Parameter
Input high level
Input low level
Input rise time
Input fall time
Input reference level
Output reference level
Output load
Conditions
V
IH
= 2.4 V
V
IL
= 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
1.4 V
Fig. 1& 2
Output Load 1
DQ
50Ω
VT = 1.4 V
30pF
1
Output Load 2
3.3 V
DQ
5pF
1
589Ω
434Ω
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1
unless otherwise noted.
3. Output load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
AC Characteristics
Read Cycle
Parameter
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Symbol
t
RC
t
AA
t
AC
t
OE
t
OH
t
LZ
*
t
OLZ
*
t
HZ
*
t
OHZ
*
-7
Min
7
—
—
—
3
3
0
—
—
Max
—
7
7
3
—
—
—
3.5
3
Min
8
—
—
—
3
3
0
—
—
-8
Max
—
8
8
3.5
—
—
—
4
3.5
Min
10
—
—
—
3
3
0
—
—
-10
Max
—
10
10
4
—
—
—
5
4
Min
12
—
—
—
3
3
0
—
—
-12
Max
—
12
12
5
—
—
—
6
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
* These parameters are sampled and are not 100% tested
Rev: 1.04a 10/2002
5/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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