NJM2211
FSK DEMODULATOR / TONE DECODER
■
GENERAL DESCRIPTION
The
NJM2211
is a monolithic phase-locked loop (PLL) system especially
designed for data communications. It is particularly well suited for FSK modem
applications, and operates over a wide frequency range of 0.01Hz to 300kHz. It
can accommodate analog signals between 2mV and 3V, and can interface with
conventional DTL, TTL and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal frequency within the passband, a quadrature
phase detector which provides carrier detection, and an FSK voltage
comparator which provides FSK demodulation. External components are used
to independently set carrier frequency, bandwidth, and output delay.
■
FEATURES
●
Wide Operating Voltage
●
Wide frequency range
●
DTL / TTL / ECL logic compatibility
●
FSK demodulation with carrier-detector
●
Wide dynamic range
●
Adjustable tracking range
●
Excellent temperature stability
●
Package Outline
●
Bipolar Technology
■
APPLICATIONS
●
FSK demodulation
●
Data synchronization
●
Tone decoding
●
FM detection
●
Carrier detection
■
PIN CONFIGURATION
■
PACKAGE OUTLINE
NJM2211D
(4.5V to 20V)
(0.01Hz to 300kHz)
(2mV to 3V
rms
)
(±1% to ±80%)
(20ppm / °C typical)
DIP14, DMP14
NJM2211M
NJM2211D
NJM2211M
Ver.2003-12-09
-1-
NJM2211
■
BLOCK DIAGRAM
■
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Input Signal Level
Power Dissipation
Operating Temperature Range
Storage Temperature Range
SYMBOL
V
+
(T
a
=25°C)
RATINGS
20
3
(DIP14)
(DMP14)
700
300
UNIT
V
Vrms
mW
mW
°C
°C
V
IN
P
D
T
opr
T
stg
-40 to +85
-40 to +125
-2-
Ver.2003-12-09
NJM2211
■
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Operating Current
Oscillator
Frequency Accuracy
Frequency Stability Temp. Coefficient
Power Supply Rejection
Upper Frequency Limit
Lowest Operating Frequency
Timing Resistor
Timing Resistor
Loop Phase Detector
Peak Output Current
Output Offset Current
Output Impedance
Maximum Voltage Swing
Quadrature Phase Detector
Peak Output Current
Output Impedance
Maximum Voltage Swing
Input Preamp
Input Impedance
Input Signal Voltage Required to Cause Limiting
Voltage Comparator
Input Impedance
Input Bias Current
Voltage Gain
Output Voltage Low
Output Leakage Current
Internal Reference
Output Voltage
Output Impedance
V
REF
Z
0
Measure at Pin 10
4.75
-
5.30
100
5.85
-
V
Ω
R
IN
I
B
G
V
V
SAT
I
LEAK
R
L
=5.1kΩ
5, 6, 7
PIN
I
C
=3mA
V
0
=12V
Measure at Pin 3 & 8
-
-
-
-
-
2
100
70
0.3
0.01
-
-
-
1.0
11
MΩ
nA
dB
V
µA
R
IN
V
IN
Meas. at Pin 2
-
-
20
2
-
-
kΩ
mVrms
I
O
Meas. at Pin 3
-
-
-
150
1.0
11
-
-
-
µA
MΩ
V
P-P
I
0
I
OS
Z
0
V
OM
Ref. to pin 10
Meas. at pin 11
±100
-
-
±4.0
±200
±2.0
1.0
±5.0
±300
-
-
-
µA
µA
MΩ
V
R
0
Operating Range
Recommended Range
5
15
-
-
2000
100
kΩ
kΩ
∆f
0
∆f
0
/
∆T
PSRR
f
0 MAX
f
0 MIN
R
1
=∞
V =12±1V
+
V =5±0.5V
R
0
=8.2kΩ, C
0
=400pF
R
0
=2MΩ, C
0
=50µF
+
(V
+
=+12V, T
a
=25°C)
SYMBOL
V
+
TEST CONDITION
MIN.
4.5
TYP.
-
5
MAX.
20
11
UNIT
V
mA
I
CC
R
0
≥
10kΩ
-
-
-
-
-
-
±1.0
±20
±0.05
±0.2
300
0.01
-
-
±1.5
-
-
%
ppm / °C
%/V
%/V
kHz
Hz
Ver.2003-12-09
-3-
NJM2211
■
EQUIVALENT CIRCUIT
■
CIRCUIT FUNCTION
●
Signal Input (Pin 2)
The input signal is AC coupled to this terminal. The internal impedance at pin 2 is 20kΩ, Recommended input signal
leveles in the range of 10mVrms to 3Vrms.
●
Quadrature Phase Detector Output (Pin 3)
This is the high-impedance output of the quadrature phase detector, and is internally connected to the input of lock-detect
voltage comparator. In tone detection applications, pin 3 is connected to ground through a parallel combination of R
D
and
C
D
(see Figure 1) to eliminate chatter at the lock-detect outputs. If this tone-detect section is not used, pin 3 can be left
open circuited.
●
Lock-Detect Output, Q (Pin 5)
The output at pin 5 is at a "high" state when the PLL is out of lock and goes to a "low" or conducting state when the PLL is
locked. It is an open collector type output and required a pull-up resistor, R
L
, to V
+
for proper operation. In the "low" state it
can sink up to 5mA of load current.
●
Lock-Detect Complement, Q (Pin 6)
The output at pin 6 is the logic complement of the lock-detect output at pin 5. This output is also an open collector type
stage which can sink 5mA of load current in the low or "on" state.
●
FSK Data Output (Pin 7)
This output is an open collector logic stage which requres a pull-up resistor, R
L
, to V
+
for proper operation. It can sink 5mA
of load current. When decoding FSK signals the FSK data output will switch to a "high"or off state for low input frequency,
and will switch to a "low" or on state for high input frequency. If no input signal is present, the logic state at pin 7 is
indeterminate.
●
FSK Comparator Input (Pin 8)
This is the high-impedance input to the FSK voltage comparator. Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase-detector output (pin 11). This data filter is formed by R
F
and C
F
of
Figure 1. The threshold voltage of the comparator is set by the internal reference voltage, V
R
, available at pin 10.
-4-
Ver.2003-12-09
NJM2211
●
Reference Voltage V
R
(Pin 10)
This pin is internally biased at the reference voltage level, V
R
; V
R
=V+ / 2-650mV. The DC voltage level at this pin forms
an internal reference for the voltage levels at pin 3, 8, 11, and 12. Pin 10 must be bypassed to ground with a 0.1µF
capacitor.
●
Loop Phase Detector Output (Pin 11)
This terminal provides a high impedance output for the loop phase-detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 1). With no input signal, or with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to V
REF
. The peak voltage swing available at the phase detector output is equal to ±V
REF
.
Figure 1. FSK & Tone Detection
●
VCO Control Input (Pin 12)
VCO free-running frequency is determined by external timing resistor, R0, connected from this terminal to ground. The
VCO free-running frequency, f
0
, is given by :
1
f
0
(
Hz
)
=
R0C0
where C0 is the timing capacitor across pins 13 and 14. For optimum temperature stability R0 must be in the range of
10kΩ to 100kΩ (see Typical Electrical Characteristics).
This terminal is a low impedance point, and is internally biased at a DC level equal to V
R
. The maximum timing current
drawn from pin 12 must be limited to
≤
3mA for proper operation of the circuit.
●
VCO Timing Capacitor (Pins 13 and 14)
VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals. C0 must
be non-polarized, and in the range of 200pF to 10µF.
●
VCO Frequency Adjustment
VCO can be fine tuned by connecting a potentiometer, R
X
, in series with R0 at pin 12 (see Figure 2)
●
VCO Free-Running Frequency, F
0
The
NJM2211
does not have a separate VCO output terminal. Instead, the VCO outputs are internally connected to the
phase-detector sections of the circuit. However, for setup or adjustment purposes, the VCO free-running frequency can
be measured at pin 3 (with C
D
disconnected) with no input and also pin 2 shorted to pin 10.
Ver.2003-12-09
-5-
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
