Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
September 28, 1999, rev. **
W170-01
Pin Definitions
Pin Name
IN
FBIN
Pin No.
2
1
Pin
Type
I
I
Pin Description
Reference Input:
The output signals will be synchronized to this signal.
Feedback Input:
This input must be fed by one of the outputs (OUT1 or OUT2) to
ensure proper functionality. If the trace between FBIN and the output pin being used
for feedback is equal in length to the traces between the outputs and the signal desti-
nations, then the signals received at the destinations will be synchronized to the REF
signal input (IN).
Output 1:
The frequency of the signal provided by this pin is determined by the feed-
back signal connected to FBIN, and the FS0:1 inputs (see
Table 1).
Output 2:
The frequency of the signal provided by this pin is one-half of the frequency
of OUT1. See
Table 1.
Power Connections:
Connect to 3.3V or 5V. This pin should be bypassed with a
0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter
performance.
Ground Connection:
Connect all grounds to the common system ground plane.
Function Select Inputs:
Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table 1.
OUT1
OUT2
VDD
6
8
7
O
O
P
GND
FS0:1
3
4, 5
P
I
Overview
The W170-01 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing max-
imum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
“How to Implement Zero Delay,” and “Inserting Other Devices
in Feedback Path.”
The W170-01 is a pin-compatible upgrade of the Cypress
W42C70-01. The W170-01 addresses some application de-
pendent problems experienced by users of the older device.
Most importantly, it addresses the tracking skew problem in-
duced by a reference which has Spread Spectrum Timing en-
abled on it.
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through,
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note titled, “EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
2
W170-01
C
A
G
10 µF
Ferrite
Bead
V+
C8
G
0.01 µF
Power Supply Connection
OUT 2
FBIN
1
8
V
DD
22Ω
OUTPUT 2
C9 = 0.1 µF
G
IN
7
2
3
GND
G
6
OUT 1
22Ω
OUTPUT 1
FS0
4
5
FS1
Figure 1. Schematic/Suggested Layout
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) are used because a de-
signer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feed back and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Referring to
Figure 2,
if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay in the ASIC/Buffer must be accounted for.
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals up to the signal coming from
Figure 2. 6 Output Buffer in the Feedback Path
3
W170-01
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
DC Electrical Characteristics
:
T
A
=0°C to 70°C, V
DD
= 3.3V ±5%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
I
OL
= 8 mA
I
OH
= 8 mA
V
IN
= 0V
V
IN
= V
DD
2.4
5
5
2.0
0.4
Test Condition
Unloaded, 133 MHz
Min
Typ
17
Max
35
0.8
Unit
mA
V
V
V
V
µA
µA
DC Electrical Characteristics
:
T
A
=0°C to 70°C, V
DD
= 5V ±10%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
I
OL
= 8 mA
I
OH
= 8 mA
V
IN
= 0V
V
IN
= V
DD
2.4
5
5
2.0
0.4
Test Condition
Unloaded, 133 MHz
Min
Typ
31
Max
50
0.8
Unit
mA
V
V
V
V
µA
µA
4
W170-01
AC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DD
= 3.3V±5%
Parameter
f
IN
f
OUT
t
R
t
F
t
ICLKR
t
ICLKF
t
PD
t
D
t
LOCK
t
JC
Description
Input Frequency
[1]
Output Frequency
Output Rise Time
Output Fall Time
Input Clock Rise Time
[2]
Input Clock Fall Time
[2]
FBIN to IN (Reference Input) Skew
[3, 4]
Duty Cycle
PLL Lock Time
Jitter, Cycle-to-Cycle
Note 4
Note 5
Power supply stable
Note 6
40
50
Test Condition
OUT2 = REF
OUT1
0.8V to 2.0V, 15-pF load
2.0V to 0.8V, 15-pF load
20
133
3.5
2.5
10
10
300
60
1.0
200
Min
Typ
Max
Unit
MHz
MHz
ns
ns
ns
ns
ps
%
ms
ps
AC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DD
= 5V±10%
Parameter
f
IN
f
OUT
t
R
t
F
t
ICLKR
t
ICLKF
t
PD
t
D
t
LOCK
t
JC
Description
Input Frequency
[1]
Output Frequency
Output Rise Time
Output Fall Time
Input Clock Rise Time
[2]
Input Clock Fall Time
[2]
FBIN to IN (Reference Input) Skew
Duty Cycle
PLL Lock Time
Jitter, Cycle-to-Cycle
[3, 4]
Test Condition
OUT2 = REF
OUT1
0.8V to 2.0V, 15-pF load
2.0V to 0.8V, 15-pF load
Min
20
Typ
Max
133
3.5
2.5
10
10
Unit
MHz
MHz
ns
ns
ns
ns
ps
%
ms
ps
Note 4
Note 7, 8
Power supply stable
Note 6
40
50
300
60
1.0
200
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. Longer input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
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