1. Operation in excess of any parameter limit (except T
BS
) may cause permanent damage to the device.
2. MTTF > 1 x 10
6
hours @ T
BS
≤ 85°C. Operation in excess of maximum operating temperature (T
BS
) will degrade MTTF.
DC Specifications/Physical Properties
(T
A
= 25°C, V
CC
– V
EE
= 5.0 volts, unless otherwise listed)
Symbol
V
CC
– V
EE
|I
CC
| or |I
EE
|
V
RFin(q)
V
RFout(q)
V
Logic
Parameters/Conditions
Operating bias supply difference
1
Bias supply current
Quiescent dc voltage appearing at all RF ports
Nominal ECL Logic Level
(V
Logic
contact self-bias voltage, generated on-chip)
Min.
4.5
37
Typ.
5.0
44
V
CC
Max.
6.5
51
Units
volts
mA
volts
V
CC
-1.45
V
CC
-1.32
V
CC
-1.25
volts
Notes
1. Prescaler will operate over full specified supply voltage range, V
CC
or V
EE
not to exceed limits specified in Absolute Maximum Ratings section.
RF Specifications
(T
A
= 25°C, Z
0
= 50 Ω, V
CC
– V
EE
= 5.0 volts)
Symbol
ƒ
in(max)
ƒ
in(min)
ƒ
Self-Osc.
P
in
Parameters/Conditions
Maximum input frequency of operation
Minimum input frequency of operation
1
(P
in
= -10 dBm)
Output Self-Oscillation Frequency
2
@ dc, (Square-wave input)
@ ƒ
in
= 500 MHz, (Sine-wave input)
ƒ
in
= 1 to 8 GHz
ƒ
in
= 8 to 10 GHz
ƒ
in
= 10 to 12 GHz
RL
S
12
φ
N
Jitter
T
r
or T
f
Small-Signal Input/Output Return Loss (@ ƒ
in
< 10 GHz)
Small-Signal Reverse Isolation (@ ƒ
in
< 10 GHz)
SSB Phase noise (@ P
in
= 0 dBm, 100 kHz offset from a
ƒ
out
= 1.2 GHz Carrier)
Input signal time variation @ zero-crossing
(ƒ
in
= 10 GHz, P
in
= -10 dBm)
Output transition time (10% to 90% rise/fall time)
-15
-15
-15
-10
-5
Min.
12
Typ.
14
0.2
3.4
> -25
> -20
> -20
> -15
> -10
15
30
-153
1
70
+10
+10
+10
+5
-1
0.5
Max.
Units
GHz
GHz
GHz
dBm
dBm
dBm
dBm
dBm
dB
dB
dBc/Hz
ps
ps
Notes
1. For sine-wave input signal. Prescaler will operate down to dc for square-wave input signal. Minimum divide frequency limited by input slew-rate.
2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Input dc offset technique described on page 4.
2
RF Specifications
(Continued)
(T
A
= 25°C, Z
0
= 50 Ω, V
CC
– V
EE
= 5.0 volts)
Symbol
P
out
3
Parameters/Conditions
@ ƒ
out
< 1 GHz
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.0 GHz
|V
out(p–p)
|
4
@ ƒ
out
< 1 GHz
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.0 GHz
P
Spitback
ƒ
out
power level appearing at RF
in
or RF
in
(@ ƒ
in
10 GHz, unused RF
out
or RF
out
unterminated)
ƒ
out
power level appearing at RF
in
or RF
in
(@ ƒ
in
= 10 GHz, both RF
out
& RF
out
terminated)
P
feedthru
H
2
Notes
3. Fundamental of output square wave's Fourier Series.
4. Square wave amplitude calculated from Pout.
Min.
-2
-3.5
-4.5
Typ.
0
-1.5
-2.5
0.5
0.42
0.37
-50
-55
-30
Max.
Units
dBm
dBm
dBm
volts
volts
volts
dBm
dBm
dBc
Power level of ƒ
in
appearing at RF
out
or RF
out
(@ ƒ
in
= 12 GHz, P
in
= 0 dBm, referred to P
in
(ƒ
in
))
Second harmonic distortion output level
(@ ƒ
out
= 3.0 GHz, referred to P
out
(ƒ
out
))
-25
dBc
Applications
The HMMC-3128 is designed for use in
high frequency communications, micro-
wave instrumentation, and EW radar
systems where low phase-noise PLL
control circuitry or broad-band frequency
translation is required.
Operation
The device is designed to operate
when driven with either a single-ended
or differential sinusoidal input signal
over a 200 MHz to 12 GHz bandwidth.
Below 200 MHz the prescaler input
is “slew-rate” limited, requiring fast
rising and falling edge speeds to
properly divide. The device will operate
at frequencies down to dc when driven
with a square-wave.
Due to the presence of an off-chip
RF-bypass capacitor inside the package
(connected to the V
CC
contact on the
device), and the unique design of the
device itself, the component may be
biased from either a single positive
or single negative supply bias. The
backside of the package is not dc
connected to any dc bias point on the
device.
For positive supply operation, V
CC
pins
are nominally biased at any voltage in
the +4.5 to +6.5 volt range with pin 8
(V
EE
) grounded. For negative bias op-
eration V
CC
pins are typically grounded
and a negative voltage between -4.5 to
-6.5 volts is applied to pin 8 (V
EE
).
AC-Coupling and DC-Blocking
All RF ports are dc connected on-chip
to the V
CC
contact through on-chip 50
Ω resistors. Under any bias condi-
tions where V
CC
is not dc grounded
the RF ports should be ac coupled via
series capacitors mounted on the PC
board at each RF port. Only under bias
conditions where V
CC
is dc grounded
(as is typical for negative bias supply
operation) may the RF ports be direct
coupled to adjacent circuitry or in
some cases, such as level shifting
to subsequent stages. In the latter
case the package heat sink may be
“floated” and bias applied as the dif-
ference between V
CC
and V
EE
.
3
Input DC Offset
If an RF signal with sufficient signal
to noise ratio is present at the RF
input lead, the prescaler will operate
and provide a divided output equal the
input frequency divided by the divide
modulus. Under certain "ideal" condi-
tions where the input is well matched
at the right input frequency, the com-
ponent may “self-oscillate”, especially
under small signal input powers or
with only noise present at the input.
This “self-oscillation” will produce a
undesired output signal also known
as a false trigger. To prevent false
triggers or self-oscillation conditions,
apply a 20 to 100 mV dc offset voltage
between the RF
in
and RF
in
ports. This
prevents noise or spurious low level
signals from triggering the divider.
Adding a 10 kΩ resistor between the
unused RF input to a contact point
at the V
EE
potential will result in an
offset of ≈ 25 mV between the RF
inputs. Note however, that the input
sensitivity will be reduced slightly due
to the presence of this offset.
Figure 1. Simplified Schematic
unused RF output lead should be ter-
minated into 50 Ω to a contact point
at the V
CC
potential or to RF ground
through a dc blocking capacitor.
A minimum RF and thermal PC board
contact area equal to or greater than
2.67 × 1.65 mm (0.105" × 0.065") with
eight 0.020" diameter plated-wall
thermal vias is recommended.
MMIC ESD precautions, handling
considerations, die attach and bond-
ing methods are critical factors in suc-
cessful GaAs MMIC performance and
reliability.
Agilent application note #54, “GaAs
MMIC ESD, Die Attach and Bonding
Guidelines” provides basic information
on these subjects.
Moisture Sensitivity Classification:
Class 1, per JESD22-A112-A.
Assembly Notes
Independent
of the bias applied to the
package, the backside of the package
should always be connected to both
a good RF ground plane and a good
thermal heat sinking region on the
PC board to optimize performance.
For single-ended output operation the
Additional References:
PN #18, "HBT Prescaler Evaluation
Board."
4
Symbol
A
A1
B
C
D
E
e
H
L
a
Min.
1.35
0.0
0.33
0.19
4.80
3.80
1.27 BSC
5.80
0.40
0°
Max.
1.75
.25
0.51
.025
5.00
4.00
1.27 BSC
6.20
1.27
8°
Notes
:
•
•
•
•
All dimensions in millimeters.
Refer to JEDEC Outline MS-012 for additional tolerances.
Exposed heat slug area on package bottom = 2.67 x 1.65.
Exposed heat sink on package bottom must be soldered to
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