SLG46140
GreenPAK
Programmable Mixed-signal Matrix
General Description
The SLG46140 GreenPAK is a one-time non-volatile memory
(NVM) Programmable Mixed-Signal Matrix designed to
implement a wide variety of mixed-signal functions in a single,
small, low-power device by integrating a number of common
discrete ICs and passive components.
Pin Configuration
GPIO
GPIO
VDD
GPI
GPIO
GPIO
GPIO
1
14
2
3
4
5
6
7
13
12
11
10
9
8
GPIO
GPIO
GPIO
GPIO
GND
Features
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Logic & Mixed Signal Circuits
Highly Versatile Macro Cells
1.8V (±5%) to 5V (±10%) Supply
Operating Temperature Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
Pb-Free: 1.6 x 2.0 x 0.55 mm, 0.4 mm pitch
GPIO
GPIO
14-pin STQFN
(Top View)
Applications
The extensive list of integrated components included in the SLG46140 can be used to implement these and many other
functions, often in combination.
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Ambient Light Detect
Battery Charge Control
Fan Control
Hall Effect Drive
LED Control
Level Shift
One-Shot Detect
Optical Encode
Over Voltage Protect
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Port Detection
Power Sequencing
Sensor Interface
Signal De-Glitch
Signal Delay
System Reset
Thermal Management
Voltage Level Detect
Silego Technology, Inc.
000-0046140-105
Rev 1.05
Revised July 3, 2017
SLG46140
Block Diagram
Pin 14
GPIO
Pin 13
GPIO
ACMP0
ACMP1
DAC0
Look Up Tables (LUTs)
2-bit
LUT2_0
2-bit
LUT2_1
3-bit
LUT3_0
3-bit
LUT3_3
Pin 11
GPIO
Combination Function Macrocells
2-bit
LUT2_2
3-bit
LUT3_1
Pin 12
GPIO
Pin 1
VDD
DAC1
Additional Logic
Functions
FILTER_0
PGA
8-bit SAR
ADC
2-bit
LUT2_3
3-bit
LUT3_2
Pin 2
GPI
POR
Pin 3
GPIO
Vref
DFF/Latches
DFF4
DFF5
2-bit
LUT2_4
or DFF0
3bit
LUT3_5
or DFF3
2-bit
LUT2_5
or DFF1
3-bit
LUT3_4
or DFF2
SPI
Pin 10
GPIO
3-bit
3-bit
LUT3_6 or LUT3_7 or
CNT3
Pipe Delay
4-bit
LUT4_1
or CNT2
Pin 9
GPIO
Pin 4
GPIO
Programmable Delay
Counters/Delay Generators
CNT0
CNT1
4bit
LUT4_0
or PGEN
Pin 5
GPIO
LF Oscillator
PWR DET
Ring Oscillator
Digital Comparators/PWMs
DCMP0
RC Oscillator
DCMP1
DCMP2
Pin 8
GND
Pin 6
GPIO
Pin 7
GPIO
000-0046140-105
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SLG46140
1.0 Overview
In addition to the integrated analog and digital components, the SLG46140 comprises an internal connection matrix and one-time
programmable NVM. By programming the NVM, using the easy-to-use GreenPAK development tools, the designer configures
the connection matrix, I/O Pins, and integrated components of the SLG46140. The SLG46140 includes the following analog and
digital resources:
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8-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC)
ADC 3-bit Programmable Gain Amplifier (PGA)
Two Digital-to-Analog Converters (DAC)
Two Analog Comparators (ACMP)
Voltage Reference (VREF)
Eight Combinatorial Lookup Tables (LUTs)
• Four 2-bit LUTs
• Four 3-bit LUTs
Nine Combination Function Macrocells
• One 14-bit Delay/Counter (Wake-Sleep Control)
• Two Selectable DFF/Latch or 2-bit LUTs
• Two Selectable DFF/Latch or 3-bit LUTs
• One Selectable 16-Stage / 3-Output Pipe Delay or 3-bit LUT
• One 8-bit Delay/Counter/Finite State Machine
• One 14-bit Delay/Counter/Finite State Machine
• One Selectable Pattern Generator or 4-bit LUT
Three Digital Comparators/Pulse Width Modulators (DCMPs /PWMs) w/ Selectable Deadband
Three Counters/Delays (CNT/DLY)
• One 14-bit Delay/Counter/Finite State Machine
• One 14-bit Delay/Counter
• One 8-bit Delay/Counter
Two D Flip-flops/Latches
Programmable Delay w/ Edge Detection
Three Internal Oscillators
• Low-Frequency
• Ring
• RC 25 kHz and 2 MHz
Power-On-Reset (POR)
Slave SPI
One Bandgap
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000-0046140-105
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SLG46140
2.0 Pin Description
2.1 Functional Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name Function
VDD
GPI
GPIO
GPIO
GPIO
GPIO
GPIO
GND
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Power Supply
General Purpose Input
General Purpose I/O or ADC Vref_IO
General Purpose I/O or Analog Comparator 0 (-) / PGA_OUT
General Purpose I/O or Analog Comparator 1 (-)
General Purpose I/O or PGA(+)
General Purpose I/O or PGA(-)
GND
General Purpose I/O or ACMP1(+)
General Purpose I/O or ACMP0(+)
General Purpose I/O or AIN MUX
General Purpose I/O
General Purpose I/O
General Purpose I/O
000-0046140-105
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SLG46140
3.0 User Programmability
The SLG46140 is a user programmable device with One-Time-Programmable (OTP) memory elements that are able to construct
combinatorial logic elements. Three of the I/O Pins provide a connection for the bit patterns into the OTP on board memory. A
programming development kit allows the user the ability to create initial devices. Once the design is finalized, the programming
code (.gpx file) is forwarded to Silego to integrate into a production process.
Figure 1. Steps to create a custom Silego GreenPAK device
000-0046140-105
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