TN0873
Technical note
DIE2HR/D2HR manufacturing and quality specification
Introduction
This specification describes the manufacturing flow and quality insurance requirements to
be fulfilled for STMicroelectronics
®
space-grade dice related to ESCC qualified products
and, with some restrictions described in the document, to any product in die form. It is
compliant with ECSS-Q-ST-60-05C and with ST internal procedure 7015397.
ST QML qualified products, available in die form, comply with the MIL-PRF-38535
specification, which provides all details on the manufacturing flow and quality insurance of
these products. QML products are not covered in this specification.
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Space-grade description
TN0873
1
1.1
Space-grade description
Eligible products
In absence of an ESCC quality system for deliveries in die form, ST has developed
a dedicated proprietary space-grade, largely inspired by the American QML specifications.
Any ESCC qualified product can be provided in die form in compliance with this
specification.
The ST space-grade can be applied to non-ESCC and non-QML qualified products. Contact
ST for further details.
1.2
Product identification
The ST space-grade can be identified by a specific suffix (either DIE2HR or D2HR) in the
ST part number.
Example: 2N2222ADIE2HR
1.3
Die layout
ST provides, upon request, a document containing the die layout and the following
mechanical information:
•
•
•
•
•
•
•
Wafer size
Die size
Die thickness
Back metallization
Top metallization
Die pad size
Die pad identification with the corresponding die layout.
1.4
Production flow
For all products with an ESCC qualified version, ST guarantees that the mask set, diffusion
plant and diffusion process of any ST space-grade die are exactly the same as for the
corresponding ESCC qualified packaged parts.
In addition, ST space-grade dice have a guaranteed diffusion lot homogeneity for each line
item of any order, i.e., ST guarantees that wafers have been processed within the same
production batch and on the same equipment, at all process steps including diffusion,
metallization and passivation.
The manufacturing flow of space-grade die is made from wafers qualified as described
above. Eligible wafers go through the production flow summarized in
Table 1.
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Space-grade description
Table 1. Summary of production flow
Step description
Electrical wafer sort
S.EM. inspection
Discrete products
100%
Bipolar transistors: 100%
MOSFET: 100%
Diodes: No
Bipolar transistors: if applicable
MOSFET: 100%
Diodes: No
100%
ESCC2045000 @ 100%
Integrated circuits
100%
100%
Comments
See
1.4.1
See
1.4.2
Radiation test
Wafer qualification
Visual test
Conditioning
Packing
100%
100%
ESCC2049000 @ 100%
See
1.4.3
See
1.4.4
See
1.4.5
See
1.4.6
See
1.4.6
Waffle pack
Vacuum sealed anti-static bag
1.4.1
Electrical wafer sort
The electrical wafer sort carried out on the parts ensures that the tested parts comply with
the functional and electrical specification of the packaged versions as described in the
datasheet.
1.4.2
S.E.M inspection
The S.E.M inspection is made in compliance with the governing specification, which
depends on the product family:
•
•
•
•
Diodes: no S.E.M inspection
Bipolar transistor: S.E.M inspection as per MIL-STD-750 method 2077 for all orders
MOSFET: S.E.M inspection as per MIL-STD-750 method 2077 for all orders
Logic and other ICs: S.E.M inspection as per MIL-STD-883 method 2018 for all orders.
For bipolar transistors and MOSFETs, an S.E.M inspection report is optional and incurs
costs. An S.E.M inspection report is provided by default with each shipment of integrated
circuits in die form with the ST space-grade.
1.4.3
Radiation test
Products with a guaranteed radiation level are qualified in radiation with the flow of their
packaged counterparts, either as per the qualifying agency specification or according to an
ST internal specification (the latter only for product without version with guaranteed radiation
level qualified as such by an agency).
The Radiation Verification Test report is provided with each shipment of radiation
guaranteed parts. The details of the test (total dose, dose rate, biasing conditions, etc) are
product family dependent.
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Space-grade description
TN0873
1.4.4
Wafer qualification
Wafers eligible for the ST space-grade level (see
Section 1.1)
are screened as described in
Table 2.
Only wafers that have been successfully screened can be used to produce dice of
the ST space-grade level.
Table 2. Space-grade level
Step #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Step definition
Samples assembly
(2)
Serialization
(4)
Conditions
According to the ST qualified PID as
applicable
n samples
Acceptance
Acceptance
(1)
level n = 38
(1)
level n = 25
(3)
(3)
Electrical test read and record As per ESCC detail specification (DC/AC
at 25 °C
parameters for ICs or DC for discrete)
Electrical test read and record As per ESCC detail specification (DC
parameters)
at -55 °C/+125 °C
(6)
Electrical test read and record As per ESCC detail specification drift
at 25 °C for drift parameters
table
High temperature reverse
bias
(6)
As per ESCC detail specification
conditions
A2/R3
(5)
A3/R4
(5)
-/-
-/-
A1/R2
-/-
A1/R2
-/-
-/-
A2/R3
-/-
A2/R3
Electrical test read and record As per ESCC detail specification drift
at 25°C for drift parameters
(6)
table
Burn-in (240 hrs)
As per ESCC detail specification
conditions
Electrical test read and record As per ESCC detail specification drift
at 25° C for drift parameters
table
Electrical test read and record As per ESCC detail specification (DC/AC
at 25 °C
parameters or DC for discrete)
Electrical test read and record As per ESCC detail specification (DC
at -55 °C/+125 °C
parameters)
Life test 1000 hrs
As per ESCC detail specification
conditions
A2/R3
A3/R4
-/-
A0/R1
A2/R3
-/-
A0/R1
A3/R4
Electrical test read and record As per ESCC detail specification end-
at 25 °C
point electrical measurements
Check for lot failure
Check from step 3 to step 11
1. Ax/Ry: accepted if x rejects or less / refused if y rejects or more.
2. According to applicable ESCC 5000 or ESCC 9000 (chart F2 and F3 up to PIND test).
3. The number of samples allows the qualification of up to 3 wafers, therefore limiting the maximum quantity of the product in
die form per line item to: 1000 dice maximum per line item for the 54HCMOS/CMOS4000B and diodes, and 5000 dice
maximum per line item for bipolar transistors. The number of samples can be increased in the Premium option. Contact ST
for the corresponding acceptance level.
4. Sample size and acceptance criteria are based on the ECSS-Q-ST-60-05C specification, with limited sample size to 25 and
38 pieces. Data provided are for the default 25 samples.
5. Electrical rejects are not counted as failures if due to the ST assembly process.
6. Electrical tests at high/low temp and/or HTRB are optional and shall be done only on customer request and specified on the
purchase order at additional cost.
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Space-grade description
1.4.5
Visual test
All products must successfully pass the applicable ESCC space level visual test:
–
–
Discrete products: ESCC2045000
Integrated circuits: ESCC2049000
1.4.6
Conditioning & packing
Dice are packed in suitable antistatic waffle packs, vacuum sealed with adequate protection
in order to avoid contamination or mechanical stress during shipment and handling.
Each waffle pack contains dice from a single wafer.
The standard orientation of dice within each waffles depends on the product, as described
below. Contact ST for specific request:
•
•
CMOS4000B - HCMOS - MOSFET: all dice within any waffle have the same
orientation. Orientation may vary from one waffle to the other.
Diodes - bipolar transistors: the size of the dice doesn't allow to guarantee a single
orientation within a waffle.
ST logo
Sales type reference
Wafer number
Diffusion lot number
Quantity of dice
ESD warning label identification.
Each waffle pack is marked as described below:
•
•
•
•
•
•
1.5
Quality requirements
All documentation or traceability information corresponding to each ST space-grade dice is
retained for 10 years in a safe storage area.
Upon request, this traceability and documentation may be reviewed by the customer or a
copy provided, submitted to a lot charge defined by the ST sales area.
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