®
AN1751
APPLICATION NOTE
EMI Filters: Recommendations and measurements
P. MERCERON AND P. RABIER
With the development of wireless telecommunications, consumer products and cellular phones are sub-
jected to Radio Frequency Interference and may generate ElectroMagnetic Interference. This is in addition
to ElectroStatic Discharge the user can apply when touching a connector like a bottom connector on a cel-
lular phone.
In the past, filtering was achieved by discrete devices (capacitors, resistors) and ESD protection was done
by discretes diodes. Cellular phone size drop and enhanced features require faster signals and more and
more integrated devices which are becoming very sensitive to ESD or EMI/RFI.
Discretes devices impose a well designed layout to minimize parasitic effect of PCB inductances while In-
tegrated Passive and Active Devices suppress most of these inductances due to very short tracks between
passives on the die itself.
Fig. 1:
Frequency response comparison between discrete and IPAD™ filter.
dB
IPAD
DISCRETES
10 MHz
100 MHz
1 GHz
Discrete filter will behave like a rejection filter but the rejection frequency will be depending on parasitic in-
ductances while the IPAD filter will act like a low pass filter.
EMIF filters have three main functions, the first is of course to filter EMI/RFI, the second is to protect inputs
and outputs against ESD and the third one is to transmit data from inputs to outputs. EMIF datasheets pro-
vide data and curve measured in specific conditions. The goal of this note is to explain test conditions for
EMIF devices.
1-Frequency response
EMIF target is to pass low frequency signals and to reject frequency higher than 800MHz especially
900MHz, 1.8 and 2.4GHz.
Attenuation curve provided in specification shows :
n
Simulation thanks to the Aplac (or P-Spice) tool. This is done before the die design to be sure the device
will fit customer requirements
n
Measurement done on demonstration board.
September 2003 - Ed: 1
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AN1751 - APPLICATION NOTE
Aplac models take into account of die, bumps and via for the ground connections. It does not consider PCB
track in the application.
Figure 2
represents an example of Aplac model for one filtering cell.
Fig. 2:
Aplac model for die, bumps and PCB via.
I1
Rs
MODEL = D01
MODEL = D02
O1
Cin
Rsubump
Cout
Rsubump
Die model
gnd
Bump model
Lbump
Rbump
Cgnd
Lgnd
Via model
Rgnd
P-Spice is probably the most wellknown simulation software in electronic industry. Limits of P-Spice is
reached when trying to simulate RF signals because of the time it takes for each simulation. It is also
impossible to simulate crosstalk phenomena. Aplac has been developed to avoid all these P-Spice
limitations.
Concerning measurements, the first step is to calibrate the equipment. This is why demoboards are
delivered with a calibration kit shown in
figure 3
while the IPAD™ device is on another board (figure
4).
Fig. 3:
Calibration board.
Fig. 4:
Measurement condition on demoboard.
50
Ω
50
Ω
Vg
If test equipment is not calibrated, non negligible error can occur as the attenuation measurement will
correspond to the one of the IPAD™ + board + connections. Furthermore measurement is done with a
50
Ω
load while some applications may have other impedances.
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AN1751 - APPLICATION NOTE
2- ESD and latch-up measurements
I/O lines of a cellular phone must be protected against ESD. Most popular ESD standard is the
IEC61000-4-2 having a surge generator defined in
figure 5.
Fig. 5:
IEC61000-4-2 generator and the result on a non protected integrated circuit die.
R1
+
C1
-
GND
L1
+
R2
L2
To pin
C2
-
GND
IEC61000-4-2 specifies C1 charged up to 8kV (contact) and 15kV (air discharge). The MIL-STD 883E
Method 3015.7 is also a reference.
All external pins (bottom connectors, microphone jack…) may be subjected to these kinds of surges. If no
protection is used, result will be the destruction of the internal silicon chip. Destroyed I/O is generally a
short circuit as silicon melt on a very small area as shown in
figure 5.
If ESD protection device is the minimun to prevent failure, layout is also very important as very high dI/dt of
surge will generate a high LdI/dt.
This means even with a protection device, an integrated circuit can be destroyed because of layout
problem.
Figure 6
explains differences between 2 layouts.
Fig. 6:
Two layouts for two very different results.
IC to be
protected
L6
V
IC
V
CL
L5
L1
L2
V
IN
L3
L4
IC to be
protected
L6
V
IC
V
CL
L1
V
IN
L3
L2
Wrong layout
Correct layout
Knowing all PCB tracks are equivalent to an inductance, in the first case the IC will see a voltage:
V
IC
= (L1+L2+L3+L4) x dI/dt + V
CL
With a track lengh, for protection device connection, of 2 cm (1cm from side to side), 35µ thickness, 0.5mm
wide (microstrip track) then L2+L3 = 8nH
Considering a 15kV ESD surge surge having dI/dt = 50A/0.7ns
The result is V
IC
= 570V
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AN1751 - APPLICATION NOTE
Overvoltage being directly linked to track lengh, voltage across IC may be much higher with few more
centimeters. Most of IC will not like it.
With the correct layout, no high current is flowing through L6 and L3, then V
IC
= V
CL
In the first case, IC can be destroyed while with the second layout IC is perfectly protected.
Figure 7
gives input and output voltages of an EMI filter with the suitable layout. The demoboard shows the
ESD is applied on input (V
IN
), while EMIF output (V
OUT
) is connected to the IC to be protected.
Fig. 7:
ESD demoboard and measurements on EMIF10-1K010F1.
ESD test board for EMI
Out
Out
®
In
E
EMI
325
GND
Vout measurement
Vin measurement
Figure 8
shows the equivalent schematic with the ESD surge generator, the EMI Filter and the load which
corresponds to the device to be protected.
Fig. 8:
Equivalent schematic of EMI filter connected to ESD surge generators.
Rg
R
I/O
Rd
Vg
Vin
V
BR
Rd
Vout
V
BR
R
Load
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AN1751 - APPLICATION NOTE
Using EMI filter, protection is done in two steps. The first ESD diode will limit the V
IN
voltage to:
V
IN
=
Rg
×
V
BR
+
Rd
×
Vg
Rg
+
Rd
R
×
V
BR
+
Rd
×
V
IN
R
I
/
O
+
Rd
V
OUT
=
Taking into account of : R >> Rd, Rg >> Rd and Rload >> Rd (open circuit on the test board).
With Vg = 15kV, Rg = 330Ω applied to the EMIF10-1K010F1 board (Rd = 1Ω , V
BR
= 8V and R
I/O
= 1kΩ )
V
IN
= 53V and V
OUT
= 8.4V
With a correct layout, maximum output voltage is closed to V
BR
.
Early ageing and destruction of IC is often due to latch-up phenomena which is mainly induced by dV/dt.
Thanks to its RC structure, EMI filters provide high immunity to latch-up by integration of fast edges.
Measurements done on
figure 7
show very clearly the high efficiency of the structure.
3- Crosstalk measurements
3a - Digital crosstalk
Crosstalk phenomena are due to coupling between 2 lines (2 filters in our case). Coupling factors (β12 and
β21)
shown in
figure 9
increase when distance between lines decreases, particularly in silicon dice where
distances between components are very short.
In the example above the expected signal on load RL2 is
α2
x Vg2, in fact the actual voltage at this point
has got an extra value
β21
x Vg1. This part of the Vg1 signal represents the effect of the crosstalk
phenomenon of the line 1 on the line 2.
This phenomenon has to be taken into account when drivers impose fast digital data or high frequency
analog signals. The disturbed line will be more affected if it works with low voltage signal or high load
impedance (few kΩ).
Fig. 9:
Crosstalk phemonema.
Rg1
Line 1
Vg1
R
L1
α
1 x Vg1 +
β
12 x Vg2
Rg2
Line 2
Vg2
R
L2
α
2 x Vg2 +
β
21 x Vg1
Drivers
Receivers
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