AN1301
APPLICATION NOTE
STE100P - SINGLE PORT FAST ETHERNET TRANSCEIVER
1.0 GENERAL DESCRIPTION
The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer interface for
10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media
Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical me-
dia interface for 100BASE-TX and 10BASE-T. The twisted pair interface directly drives a 10/100 twisted pair
connection. STE100P is an excellent device perfectly suited for hub, switch, router and other embedded Ether-
net applications.
The system diagram is as shown below:
Figure 1. System Diagram of the STE100P Application
S e ria l
EEPROM
LED s
PCI Interface
M AC
D ev ic e
S TE 100P
STEPHY1
Transformer
R J -4 5
Boot RO M
25 M H z
C r y s ta l
2.0 FEATURES
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Integrates the whole physical layer functions of the 100BASE-TX and 10BASE-T
3.3V low power operation
The hardware control pins set the initial state of the STE100P at power-up
Designed with a power down feature, which can save the power consumption significantly
Can operate for either full duplex or half duplex network applications.
MII interface
Provides auto-negotiation, parallel detection or manual control for mode setting
Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
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November 2003
AN1301 APPLICATION NOTE
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Provides transmit wave-shaper, receive filters, and adaptive equalizer
Provides loop-back modes for diagnostic testing
Builds in Stream Cipher Scrambler/Descrambler and 4B/5B encoder/decoder
Supports external transmit transformer with turn ratio 1:1
Supports external receive transformer with turn ratio 1:1
3.0 DESIGN AND LAYOUT GUIDELINES
3.1 General Guidelines
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Verify that all components meet application requirements.
Design in filters for the analog power circuits.
Use bulk capacitors (10-22uF) between the power and ground planes to minimize switching noise, par-
ticularly near high-speed busses (>25 MHz).
Use an ample supply of 0.1uF decoupling capacitors to reduce high-frequency noise on the power and
ground planes.
Use a single analog power and ground plane for multiple devices. Keep ferrite bead currents under 65%
of the rated load
Avoid breaks in the ground plane, especially in areas where it is shielding high-frequency signals.
Keep power and ground noise levels below 50mV
Keep high-speed signals out of the area between STE100P and the magnetics
Ensure that the power supply is rated for the load and that output ripple is minimal (<50mV)
Route high-speed signals next to a continuous, unbroken ground plane.
Provide impedance matching on long traces to prevent reflections.
Do not route any digital signals between the STE100P and the RJ-45 connectors at the edge of the
board
It is recommended to fill in unused areas of the signal planes with solid copper and attach them with
vias to a Vcc or ground plane that is not located adjacent to the signal layer.
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3.2 Differential Signal Layout Guidelines
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Route differential pairs close together and away from everything else
Keep both traces of each differential pair as close to the same length as possible.
Avoid vias and layer changes
Keep transmit and receive pairs away from each other. Run orthogonally, or separate with a ground
plane layer.
3.3 Power and Ground
In order to obtain high speed communications design, the power and ground planes may be conceptually divid-
ed into three regions (the analog and digital power planes and the signal ground plane)
The analog power region extends from the magnetics back to the STE100P, whereas the digital power region
extends from the MII interfaces of the STE100P through the rest of the board. Only components and signals
pertaining to the particular interface should be placed or routed through each respective region. The digital sec-
tion supplies power to the digital Vcce/i pin and to the external components. The analog section supplies power
to Vcca pins of the STE100P.
The signal ground region is one continuous, unbroken plane that extends from the magnetics through the rest
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AN1301 APPLICATION NOTE
of the board. The signal ground plane may be combined with chassis ground or isolated from it. If the ground
planes are combined, an isolation area is not required. When laying out ground planes, special care must be
taken to avoid creating loop antenna effect. Some guidelines are as follows-
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Run all ground plane as solid square or rectangular regions
Avoid creating loops with ground planes around other planes
3.4 Recommendations
The following recommendations apply to design and layout of the power and ground planes and will prevent the
most common signal and noise issues.
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Divide the Vcc plane into two sections - analog and digital. The break between the planes should run
under the device.
When dividing the Vcc plane, it is not necessary to add extra layers to the board. Simply crate moats or
cutout regions in existing layers.
Place a high-frequency bypass cap (0.1uF) near each analog Vcc pin
Join the digital and analog sections at one or more points by ferric beads. Ensure that the maximum
current rating of the bead is at least 150% of the nominal current that is expected to flow through it.
(250mA per STE100P)
Place a bulk capacitor (22uF) on each side of each ferrite bead to stop switching noise from travelling
through the ferrite.
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For designs with multiple STE100P’s, it is acceptable to supply all from one analog Vcc plane. This plane can
be joined to the digital Vcc plane at multiple points, with a ferrite bead at each one.
4.0 TWISTED PAIR INTERFACE
4.1 Transmit Interface Circuitry
Figure 2 shows a typical transmit interface circuitry. Current is sourced by the AVddt output to the centertap of
the primary side of the winding. Current flows from the centertap to TX+ and TX-. Other components are as fol-
lows:
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R1 and R2 are 49.9 ohm resistors that provide impedance matching to the line, which has a nominal
impedance of 100 ohm.
C1 shunts any common-mode energy present in the output to ground.
The magnetics consists of the main winding and a common-mode choke.
The common-mode choke stops common mode energy from reaching the line. It works together with
capacitor C1 to direct common-mode energy away from the line.
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AN1301 APPLICATION NOTE
Figure 2. Transmit Interface Circuitry
4.2 Receive Termination Circuitry
The receive termination circuit as shown in Figure 3 is a simple 100 ohm, 1% resistor across the RX+/
RX- pair. The receive circuit consists of magnetics, which include a main winding and a common-mode
choke, and termination resistance to match the line impedance. The common-mode choke can be
located on either the primary or secondary side of the winding. Some vendors place the receive com-
mon-mode choke on the line-side (primary) of the main winding while others place it on the device side
(secondary). Either location is acceptable.
Figure 3. Receive Interface Circuitry
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AN1301 APPLICATION NOTE
4.3 Standard termination
ST recommends a standard termination for the unused pairs on the twisted-pair interface as shown in
Figure 4. The termination basically looks like a 100 ohm load, matched to the line, which is by passed to
chassis ground. This termination is added for robustness and noise reduction.
Figure 4. Suggested Termination Circuit
5.0 CRYSTAL REQUIREMENTS
The crystal to be used with the STE101P should be a 25 MHz fundamental mode crystal operating in par-
allel resonance, connected as shown in the sample application circuit schematic (see section 7.1). The
following table shows the specifications for the crystal:
Parameter
Frequency
Frequency Stability
Load Capacitance
Shunt Capacitance
Units
MHz
ppm
pF
pF
8
Min
-
-
Max
-
+ 50
Nom
25.0
-
18
Table 1
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