AN2503
Application note
PDP Power Devices
Introduction
This application note discusses how to select optimal power devices and control circuitry for
alternating plasma display panel applications, concentrating on power circuits used to
sustain plasma discharge on the panel.
Plasma Display Panels (PDP) are emerging as the leading candidate for large area wall-
hanging color TVs and HDTVs [1.]. Its large screen, wide viewing angle, and thinness have
given it the edge over conventional displays. Scan, Energy Recovery (ERC) and Sustain
(discharge) circuits are important blocks that fulfill important energy saving requirements.
May 2007
Rev 1
1/30
www.st.com
Contents
AN2503
Contents
1
2
PDP Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PDP basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
PDP cell structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Panel memory characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PDP driving sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
PDP Sustain circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Sustain circuit operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1
3.1.2
3.1.3
3.1.4
Positive pulse of Vyx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Positive discharge and clamping phase . . . . . . . . . . . . . . . . . . . . . . . . . 13
Vyx back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
3.3
Symmetrical Y - X phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
PDP Power Devices characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Power devices from ST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Measurement set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Energy recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Discharge section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Path section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Set - reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
4.3
4.4
Driving section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Gate driver devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.1
Totem pole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input buffer section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
6
7
8
2/30
Bill of material and schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AN2503
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
PDP module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Cell structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory effect - no charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory effect - address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory effect - Wall charges deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory effect - discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory effect - wall charges deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory effect - discharge with reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Subfield structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Subfield structure – expression of gray level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sustain circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Circuit scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Circuit scheme – positive pulse of V
yx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Circuit scheme – positive discharge and clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit scheme – V
yx
back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Circuit scheme – clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Circuit scheme – negative pulse of V
yx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Circuit scheme – negative discharge and clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Circuit scheme – V
yx
back to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Circuit scheme – clamping to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Circuit scheme – set and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inductor current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Gate driver topology with L6385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Gate driver topology – L6388 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STS01DTP06 Totem pole. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Board schematic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Board schematic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/30
PDP Module structure
AN2503
1
PDP Module structure
Power supply, address buffer, logic and scan buffer boards are the fundamental blocks of a
PDP. In particular, the energy recovery and sustain function are performed by the Y and X
drive boards. Power MOSFETs, IGBTs, Diodes and Drivers are key products for ERC and
sustain both in X and in Y drive boards. These products are also used for the path, set-reset
function in the Y drive board only. Path switches are mandatory to isolate ERC and Sustain
switches from the negative voltage applied to the display during the scan phase, while, set
and reset switches determine identical initial condition of the plasma cells before each
address cycle.
Figure 1.
PDP module structure
ST's extensive portfolio covers the whole solution for an energy recovery circuit (ERC),
sustain circuit, path circuit, and set-reset circuit, both from a power device and IC driver
perspective.
The ST solution takes into account all fundamental requirements like cost, component
count, reliability and power consumption.
Reduced power losses and higher switching frequency are the main benefits of ST's
advanced technology.
4/30
AN2503
PDP basic
2
PDP basic
Basic knowledge on Plasma Display Panel encompasses manufacturing issues in cell
structure, physics principle in the memory effect, and display algorithms needed to create a
range of colors.
2.1
PDP cell structure
Figure 2
shows the structure of a plasma display glass panel, [2.].
Figure 2.
Cell structure
An AC PDP display is composed of front and rear glass substrates sandwiched together and
then sealed. The air is vacuumed out and a mixture of inert gases (Ne and Xe) is injected
between the glass substrates. The separation between the two opposing substrates is about
100um and the space between them is filled with a gas mixture of Ne and Xe. The front
glass substrate has a first electrode (X electrode) and a second electrode (Y electrode)
which operate as sustain electrodes. The X and Y electrodes are coated with bus
electrodes, dielectric layer, and MgO layer in sequence. The MgO protects the dielectric
from plasma damage and also aids the plasma in sustaining a discharge through secondary
electron emission from its surface. In addition, equivalent capacitor exists between the X
and Y electrodes. On the surface of the rear glass substrate, as opposed to the front glass
substrate, a third electrode operating as an address electrode (A electrode) is formed to be
orthogonal to the X and Y electrodes. Electrically, the entire assembly can now be
considered as a three-electrode capacitor. A cross point is formed where the X, Y and A
electrodes meet. Three adjacent red, blue and green cross points form a color picture
element (pixel) of the panel. In operation, an AC voltage sufficiently high will ionize the gas
to create the plasma. Then, the ultraviolet light from the plasma excites the phosphor to
create the color image.
Each pixel can be independently controlled and can assume different color gradations. The
number of pixels available determines the resolution of the glass panel vertically and
horizontally.
5/30
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