AN3161
Application note
Using the STGW35HF60WD advanced PT IGBT in parallel
Introduction
When two or more IGBTs are connected in parallel to improve the total efficiency in high
output power systems, special care is required to ensure that current sharing between the
devices is as equal as possible. Current sharing is mainly influenced by differences in IGBT
static parameters, circuitry layout (both driving and power) and thermal imbalances. All of
these elements must be considered, especially when PT (punch-through) IGBTs work in
parallel, due to their negative V
CE(sat)
coefficient. In order to provide the most efficient IGBT
to the market while supporting reliable and easier paralleling for higher power level
applications, ST offers the STGW35HF60WD 35 A, 600 V ultra fast IGBT with V
CE(sat)
selection. This device is explained in greater detail in
Section 3: New advanced planar PT
STGW35HF60WD.
May 2010
Doc ID 17151 Rev 1
1/14
www.st.com
Contents
AN3161
Contents
1
Saturation voltage impact on parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
PT, NPT and trench field stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
General guidelines on paralleling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
Thermal system impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
New advanced planar PT STGW35HF60WD . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
Notes on technology and V
CE(sat)
grouping . . . . . . . . . . . . . . . . . . . . . . . . 7
E
OFF
impact on parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
5
6
The STGW35HF60WD on the test bench . . . . . . . . . . . . . . . . . . . . . . . . . 9
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Doc ID 17151 Rev 1
AN3161
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
∆I
C
(@T
J
= 25 °C) of two paralleled IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
∆I
C
(@T
J
> 25 °C) of two paralleled IGBT without negative feedback . . . . . . . . . . . . . . . . . 5
Static V
CE(sat)
(@20 A,15 V) derating for STGW35HF60WD . . . . . . . . . . . . . . . . . . . . . . . . 7
E
OFF
vs. V
CE(sat)
for the STGW35HF60WD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC-DC boost scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
CE(sat)
(@20 A, 25 °C, 15 V) grouping for the STGW35HF60WD . . . . . . . . . . . . . . . . . . . . 9
∆I
C
at T
C
= 25 °C (board startup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
∆I
C
at T
C
= 100 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
∆I
C
at T
C
= 25 °C (board startup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
∆I
C
at T
C
= 100 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
∆I
C
at T
C
= 25 °C (board startup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
∆I
C
at T
C
= 100 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Doc ID 17151 Rev 1
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Saturation voltage impact on parallel
AN3161
1
1.1
Saturation voltage impact on parallel
PT, NPT and trench field stop
PT IGBTs (including those offered by STMicroelectronics) have typically negative V
CE(sat)
coefficients at current operative levels. This has a very important effect when two devices
work in parallel. Due to their difference in static output characteristics, the one with the
lowest static V
CE(sat)
carries more current than the other, as shown in
Figure 1.
The
∆I
C
is
the static current difference established at the beginning.
Figure 1.
∆I
C
(@T
J
= 25 °C) of two paralleled IGBT
I
CTOT
=I
C1
+I
C2
I
c
collector current (A)
I
C1
I
C2
ΔI
C
V
CE1
=V
CE2
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
V
ce
collector emitter voltage (V)
AM06441v1
Assuming the same T
J
at the beginning, the IGBT carrying higher current dissipates more
power than the other, and its T
J
increases. As a consequence, its V
CE(sat)
decreases and
the current of the IGBT increases further. The IGBT carrying less current also decreases its
static V
CE(sat)
as a consequence of the common V
CE
, and its current must satisfy the
following equation:
Equation 1
I
CTOT
=
I
C1
(
T1
)
+
I
C2
(
T2
)
4/14
Doc ID 17151 Rev 1
AN3161
Figure 2.
Saturation voltage impact on parallel
∆I
C
(@T
J
> 25 °C) of two paralleled IGBT without negative feedback
I
CTOT
=I
C(T1)
+I
C(T2)
I
c
collector current (A)
Tj>25°C,
V
GE
=15V
I
C2
ΔI
C
I
C1
V
CE1
=V
CE2
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
AM06440v1
V
ce
collector emitter voltage (V)
As a consequence of the negative V
CE(sat)
coefficient, a higher
∆I
C
is established at high T
J
(Figure
2).
This can cause thermal instability if an accurate negative feedback is not
implemented. NPT and field stop IGBTs have positive V
CE(sat)
coefficients (the latter
typically starting from low current levels). When working in parallel the one carrying the
higher current increases its temperature, which causes a V
CE(sat)
increase. This means that,
at the same on-state voltage level, the current does not increase with temperature as in PT
IGBTs; this guarantees an intrinsic balancing mechanism, preventing thermal runaway.
Doc ID 17151 Rev 1
5/14
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