AN2842
Application note
Paralleling of power MOSFETs in PFC topology
Introduction
The current handling capability demands on power supply systems to meet high load
current requirements and provide greater margins for overload and reliability, often exceed
the capability of the largest semiconductor devices considered, and their paralleling may
become an attractive alternative. All semiconductor circuits using parallel connected devices
to switch to higher load currents can easily be analyzed by using Kirchoff's law. As long as
all voltage drops in the parallel branches are equal, the currents through the branches are of
similar values if the resistance in each branch is the same. This is logical, but when we
consider the various functions where switching devices are employed, we must also
consider the parameters of each single switching device and all the parasitic phenomena
related to the device.
In this paper we review several factors that influence the behaviors of devices in parallel
configurations. When devices operate in parallel configurations to provide a good dynamic
equilibrium among device currents, consideration should be given to current sharing. The
layout design must be carried out carefully to minimize the differences between device
branches. In addition, switching parameters of devices may not be the same, causing one to
be continuously stressed (by at some time supporting all the input current). Naturally, this
problem worsens as the number of paralleled devices increases. Therefore, it is very
important to understand which factors are linked to the device that cause current imbalance.
Concerning power MOSFET devices, there are many parameters that can influence the
current imbalance and in principle they can be summarized as threshold voltage, gain,
intrinsic capacitances, ON resistance and working temperature mismatches. Individually or
in combination, mismatch between these parameters may produce serious imbalances and
could cause device failure.
In order to investigate the impact of the different factors, some PFC topologies have been
analyzed. The study has included different topologies to understand if the device behaviors
are also related to the configuration. In this paper, three booster PFC topologies are
discussed. In the first topology, a booster PFC is developed using two power MOSFETs
connected directly in parallel (Figure
1).
In this case, two different drive circuits are used for
each single device. Another topology under analysis uses two PFC blocks connected in
parallel (Figure
2).
Also in this case, two drive circuits pilot the gate pin. Finally, a topology
with three devices connected in a parallel configuration is analyzed (Figure
3).
July 2009
Doc ID 15110 Rev 1
1/22
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Contents
AN2842
Contents
1
2
Schematic diagrams of analyzed topologies . . . . . . . . . . . . . . . . . . . . . 4
Approach to the study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Differences between the power circuit components . . . . . . . . . . . . . . . . . . 5
Gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Influence of the boost diode in the current imbalance . . . . . . . . . . . . . . . 11
Temperature imbalance between devices . . . . . . . . . . . . . . . . . . . . . . . . 13
Influence of the differences between the power circuit components . . . . 13
Differences in the V
GS(th) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Differences in R
DS(on)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Influence of the g
fs
parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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AN2842
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Two MOSFETs connected in parallel with a single boost inductor . . . . . . . . . . . . . . . . . . . . 4
Two MOSFETs connected in parallel with a different boost inductor . . . . . . . . . . . . . . . . . . 4
Three MOSFETs connected in parallel with a single boost inductor . . . . . . . . . . . . . . . . . . 4
Parasitic inductance in a circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Details of current imbalance during turn-on due to external parasitic inductances . . . . . . . 6
Details of current imbalance during steady state operation due to the layout . . . . . . . . . . . 7
Current imbalance due to layout during steady state operation when the device
position is changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Details of current balance when circuit has very similar parameters . . . . . . . . . . . . . . . . . . 8
Details of current imbalance during turn-on due principally at the voltage on
the gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Details of current imbalance during turn-on when the voltage on the gate
circuitry is very comparable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Details of current imbalance during turn-off due principally to the voltage
on the gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Details of current imbalance during turn-off when the voltage on the gate
circuitry is very comparable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Contribution of the current spike value during the turn-on phase . . . . . . . . . . . . . . . . . . . . 11
Current spike during the turn-on phase when a fast diode is used. . . . . . . . . . . . . . . . . . . 12
Current spike during the turn-on phase when an ultra fast diode is used. . . . . . . . . . . . . . 12
Instant of failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Schematics of two devices connected in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Details of current imbalance during turn-on when there is a difference in V
GS(th)
value . . 15
Details of current imbalance during turn-off when there is a difference in V
GS(th)
value . . 16
Details of current imbalance due to a difference in R
DS(on)
value . . . . . . . . . . . . . . . . . . . 17
g
fs
curves for devices with comparable g
fs
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
g
fs
curves for devices with different g
fs
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Details of current imbalance during turn-on with low g
fs
spread . . . . . . . . . . . . . . . . . . . . . 19
Details of current imbalance during turn-on with high g
fs
spread . . . . . . . . . . . . . . . . . . . . 19
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Schematic diagrams of analyzed topologies
AN2842
1
Schematic diagrams of analyzed topologies
The following schematics show the three booster PFC topologies discussed in this
application note.
Figure 1.
Two MOSFETs connected in parallel with a single boost inductor
Figure 2.
Two MOSFETs connected in parallel with a different boost inductor
Figure 3.
Three MOSFETs connected in parallel with a single boost inductor
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AN2842
Approach to the study
2
Approach to the study
To better understand the factors that cause current imbalance, it is important to divide the
analysis into two different areas: in the first, we study the influence of the parameters around
the power device, while in the second we analyze the impact of the intrinsic parameters of
the power MOSFET. The parameters analyzed in the first approach are:
●
●
●
●
differences between the power circuit components
gate circuitry
influence of the boost diode in the current imbalance
temperature imbalance between devices
In the second part, we analyze the parameters linked directly to the power MOSFET, and in
particular:
●
●
●
differences in the V
GS(th)
differences of R
DS(on)
influence of the g
fs
parameter
2.1
Differences between the power circuit components
The primary contributors to current imbalance in power circuits are different drain or branch
inductance and common source inductance. These "parasitic" inductances (labeled as Lp in
Figure 4)
are mainly generated by interconnection wiring and discrete components and
have different effects depending on where they are situated. Thus the variation between
branches is a function of layout symmetry and production tolerance. If we analyze a system
that uses devices with similar electrical characteristics, the different device behaviors are
linked to external parameters.
Figure 4.
Parasitic inductance in a circuit
The impact due to the inductance in series to the gate terminal during the turn-on operation
is a delay of the event. In fact, when the signal coming to the driver is applied to the gate, the
inductance Lp in series generates an extra voltage that decreases the real voltage on the
gate pin and consequently causes a delay of the operation. The same delay effects during
turn-on are caused by the parasitic inductances on the drain and source pins. Also during
turn-off operation, the impact due to the parasitic inductances is to generate a delay of the
commutations. In the following figure, we can see how an external inductance introduced on
the gate pin generates a delay on the drain current.
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