AN2344
Application Note
Power MOSFET avalanche characteristics and ratings
Introduction
Back in the mid-80s, power MOSFET manufacturers started to claim a new outstanding
feature: Avalanche Ruggedness.
Suddenly, new families of devices evolved, all with this “new” feature. The implementation
was quite simple: the vertical MOSFET structure has an integral body drain diode which
cannot be eliminated. By changing some process and layout parameters, it is possible to
guarantee the use of the clamping capability of this diode for withstanding accidental
voltage/power surges beyond the nominal drain source voltage.
Rating ‘ruggedness’ in a datasheet was very difficult because of the great confusion
regarding the meaning of this feature, as well as poor theoretical knowledge of it.
Nonetheless, all of the Power MOSFET manufacturers started to produce avalanche-rated
devices and propose datasheet ratings (although imperfect), to protect themselves and the
end users from this incomplete knowledge.
Now, knowledge about a device’s behavior during avalanche conditions is greatly enhanced
by a number of application notes and papers issued, which provide different explanations of
avalanche ratings and behavior. This application note briefly reviews the MOSFET physics
on avalanche behavior and supplies designers with tools and suggestions for dealing with
avalanche issues.
August 2006
Rev 1
1/27
www.st.com
Contents
AN2344
Contents
1
MOSFET fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Failure modes descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
3
Testing avalanche ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Datasheet avalanche ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
Avalanche operation maximum current (IAR) . . . . . . . . . . . . . . . . . . . . . . 10
Energy during avalanche for single pulse (EAS) . . . . . . . . . . . . . . . . . . . 10
Avalanche rating example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1
EAR (Energy during avalanche for repetitive pulse) . . . . . . . . . . . . . . . 14
4
5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
AN2344
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
MOSFET vertical structure and parasitic elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
UIS reference diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical UIS waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Constant current avalanche fixture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Disconnected supply UIS fixture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EAS vs temperature STP9NK80Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Triangular pulse thermal response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
BVDSS vs ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VDS/ID shapes with the Coil during the UIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Modeling triangular pulses using rectangular pulses example . . . . . . . . . . . . . . . . . . . . . . 16
Triangular-to-rectangular pulse superimposition principle application . . . . . . . . . . . . . . . . 16
Thermal response comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Steady-state STP11NM60FP switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STP11NM60FP switch-OFF details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STP11NM60FP switch-ON details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Normalized STP11NM60FP impedante . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STP11NM60FP rectangular pulse switching approximation. . . . . . . . . . . . . . . . . . . . . . . . 21
STP11NM60FP rectangular pulse superimposition principle graph . . . . . . . . . . . . . . . . . . 22
Equally spaced, same amplitude pulse train timing diagram . . . . . . . . . . . . . . . . . . . . . . . 22
Rectangular approximation of ramp curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rectangular approximation of triangular curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rectangular approximation of parabolic curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/27
List of tables
AN2344
List of tables
Table 1.
Table 2.
Table 3.
UIS circuit equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Rectangular approximation of special power curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4/27
AN2344
MOSFET fundamentals
1
MOSFET fundamentals
Figure 1.
shows a basic, simplified MOSFET structure. The actual MOSFET is an infinite
parallel of these 'microscopic ' structures that work together, sharing the same Drain with all
of the Gates which are connected together by a deposited polysilicon mesh, and all of the
Sources are linked by the top metal layer.
In this case, the ‘mesh’ is the ST-patented, high voltage Mesh Overlay™ technology, which
optimizes the body-drain junction shape as well as improves other aspects of the MOSFET
structure. However, the overall concept of this vertical structure can be considered valid for
various older technologies (e.g. cellular) as well.
During the ON state, while the gate source voltage is above the threshold, the conduction
current is localized in the drain and the region below the gate (channel). During the OFF
state, the voltage drop across the drain and source is sustained by the PN junction at
reverse bias, and a very small current (leakage) flows through the junction.
If the voltage increases too much and the electrical field reaches the critical value, the
junction goes into breakdown, and the current starts to flow through the body region. If an
overvoltage is applied to the junction, a current flows through it while the MOSFET limits the
actual drain-source breakdown voltage.
The breakdown mechanism itself is not destructive for a PN junction. However, overheating
caused by the high breakdown current and voltage damages the PN junction unless
sufficient heat sinking is provided.
Looking at the MOSFET structure, one can see that the PN junction is not a simple or
perfect diode. The MOSFET diode is the collector-base junction of a Bipolar Junction
Transistor (BJT), also called the parasitic transistor, made by the N
+
region of source, P/P+
region of the body, and N
+
region of the drain, with the base shorted to the emitter by the
front metal.
The capability of a MOSFET to withstand the avalanche condition takes into account these
concerns. In fact, two kinds of failure arise: one is related to current, and the other to power
dissipation. In the former, failure is caused by the latching of the parasitic bipolar due to the
current that flows through its base resistance, multiplied by the gain. The second is reached
when the temperature of the junction rises to a critical value that provokes the formation of
hot spots caused by regenerative thermal runaway, with average temperatures of about
650°C, that peak at approximately 1000°C, which then triggers extremely rapid device
destruction.
Figure 1.
MOSFET vertical structure and parasitic elements
P
5/27
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