AN4671
Application note
How to fine tune your SiC MOSFET gate driver
to minimize losses
L. Abbatelli, C. Brusca, G. Catalisano
Introduction
Power electronics today is about the constant pursuit of efficiency improvements as well as cost and
size reduction.
In this challenging power conversion scenario, silicon carbide (SiC) power switches are gaining
prominence: for 1200 V power switches, silicon carbide MOSFETs are becoming an increasingly viable
alternative to conventional silicon technologies. The advanced and innovative properties of wide band-
gap materials help ensure that ST’s SiC MOSFETs exhibit low on-state resistance*area in comparison
with silicon MOSFETs, even at high temperatures, and excellent switching performance versus the best-
in-class 1200 V IGBTs in all temperature ranges, thus simplifying the thermal design of power electronic
systems.
With far lower switching losses than for comparable Si-based switches, SiC devices can operate at
switching frequencies two to five times greater than present devices and overall system designs can
also benefit from smaller and lighter passive components. The very low leakage currents boost system
reliability and consistency even when subject to elevated reverse voltages or temperature increases.
This all means that the efficiency delivered by a SiC MOSFET in any application is significantly higher
than silicon-based solutions, especially at high frequencies.
It is therefore crucial to drive SiC MOSFETs in such a way as to facilitate lowest possible conduction
and switching losses, which is why this document explains the main principles for obtaining the best
performance from ST’s 1200 V SiC MOSFET in your application.
The first ST SiC MOSFET given is the 80 mΩ version (SCT30N120), the device is packaged in the
proprietary HiP247™ package and features the industry’s highest junction temperature rating of 200 °C.
All the data reported in the present work refers to the SCT30N120.
April 2015
DocID027654 Rev 1
1/17
www.st.com
Contents
AN4671
Contents
1
2
How to minimize conduction losses .............................................. 3
How to minimize switching losses ................................................. 4
2.1
2.2
2.3
2.4
Turn-off energy (E
off
) dependence on R
g
and V
gs-off
.......................... 5
Turn-on energy (E
on
) vs. R
g
............................................................... 8
Miller effect on E
on
and E
rr
................................................................. 9
Gate drive current requirements...................................................... 11
3
4
5
Gate driver specs and implementation ........................................ 13
References ..................................................................................... 15
Revision history ............................................................................ 16
2/17
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AN4671
How to minimize conduction losses
1
How to minimize conduction losses
SiC MOSFETs require a higher gate voltage swing than standard super-junction MOSFETs
or IGBTs. We recommend a +20 V positive bias gate drive to minimize R
DS(on)
and hence
conduction losses.
It is therefore evident that SiC MOSFETs offer clear advantages over other SiC devices in
terms of:
•
•
DC current requirements – it does not require any gate current to sustain the
conduction state
simplified driving circuits – only gate resistors and a simple 0 to 20 V input waveform
are needed
It is unnecessary and even undesirable to drive SiC MOSFETs with more than +20 V in the
positive direction as the V
GS
absolute maximum rating is +25 V. It is possible to go as low
as +18 V, but this increases the R
DS(on)
by about 25% at 20 A, 25 °C. The possibility of
using a negative bias gate voltage to completely turn-off the device is treated in the
following section dedicated to the switching loss minimization.
Figure 1: SCT30N120 output characteristics (T
j
= 25 °C)
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How to minimize switching losses
AN4671
2
How to minimize switching losses
SiC MOSFETs are tailored for easy-to-drive devices, able to operate at up to five times the
switching frequency of comparable IGBTs, resulting in more compact, reliable and efficient
designs for applications such as solar inverters, high-voltage power supplies and high
efficiency drives.
To optimize switching perfomrance, a key factor in achieving the “quantum leap” in power
electronics, certain unique operating characteristics need to be understood and
implemented.
The main aspects influencing switching behavior are:
•
•
•
•
turn-off energy (E
off
) dependence on R
g
and V
GS-off
(negative bias gate voltage)
turn-on energy (E
on
) dependence on R
g
Miller effect, which affects E
on
and E
rr
(reverse recovery energy)
gate drive current requirements
All tests are subject to the V
GS-on
= +20 V condition for the reasons discussed in the
previous section. The results regarding the above mentioned parameters can be extended
to the entire SiC MOSFET family, except for gate current requirements that strongly
depend on the device current rating associated with the gate charge magnitude.
4/17
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AN4671
How to minimize switching losses
Figure 2: SiC MOSFET dynamic characterization test circuit
2.1
Turn-off energy (E
off
) dependence on R
g
and V
gs-off
As with any majority carrier device, SiC MOSFETs have no tail, so the turn-off switching
energy (E
off
) is due to the overlap between the drain-source voltage and drain current
during the voltage rise time and the current fall time.
Turn-off losses inherently depend on the device itself (as opposed to turn-on switching
losses, which can depend on the reverse recovery charge of an external silicon or SiC
diode, as in BOOST converters and many other topologies), hence the unrivaled turn-off
speed of the SiC MOSFET is a feature of this new technology that separates it from other
1200 V power actuators.
E
off
can be lowered by draining more current from the gate, by either:
•
•
reducing the gate resistance (R
g
)
using a negative bias gate voltage during off time
The SCT30N120 E
off
dependence on gate resistance is illustrated below.
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