AN975
APPLICATION NOTE
UPGRADING FROM ST625X/6XB TO ST625X/6XC
by Microcontroller Application Team
INTRODUCTION
As part of a process of continuous improvement, STMicroelectronics has replaced all
ST62T5XB and ST62T6XB devices by ST62T5XC and ST62T6XC.
This opportunity was taken to include new features such as the Low Voltage Detector (LVD)
for safe reset, the Oscillator Safeguard (OSG) and a new RC oscillator.
This application note details these new features and draws attention to some precautions that
it is mandatory to take when upgrading an application developed with B revision to C revision
devices. The first part of the document is related to the silicon itself and the second one to the
development tools.
AN975/0600
1/11
1
UPGRADING FROM ST625X/6XB TO ST625X/6XC
1 SILICON CHANGES
1.1 NEW FEATURES
1.1.1 LOW VOLTAGE DETECTOR (LVD)
ST625X/6XC now features an on-chip Low Voltage Detector which is enabled by setting a bit
in the option bytes (refer to the Option Bytes section in the device data sheet).
The LVD allows the device to be used without any external RESET circuitry. In this case, the
RESET pin should be left
unconnected.
When the LVD is not activated, an external circuit is
mandatory to ensure correct Power On Reset operation. For more details, please refer to the
application note AN669.
The LVD generates a static Reset when the supply voltage is below a reference value. This
means that it secures the power-up as well as the power-down keeping the ST6 in reset.
The V
IT-
reference value for a voltage drop is lower than the V
IT+
reference value for power-on
in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply
(hysteresis). The LVD Reset circuitry generates a reset when V
DD
is below:
– V
IT+
when V
DD
is rising
– V
IT-
when V
DD
is falling
The LVD function is illustrated in Figure 1.
If the LVD is enabled, the MCU can be in only one of two states:
– Over the input threshold voltage, it is running under full software control
– Below the input threshold voltage, it is in static safe reset
In these conditions, secure operation is guaranteed without the need for external reset hard-
ware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
2/11
2
UPGRADING FROM ST625X/6XB TO ST625X/6XC
Figure 1. Low Voltage Detector Reset
V
DD
V
hyst
V
IT+
V
IT-
RESET
1.1.2 Oscillator Safeguard (OSG)
The Oscillator Safeguard (OSG) feature is a means of dramatically improving the operational
integrity of the MCU.The OSG function is enabled by setting the OSG option bit in the Option
Byte (refer to the Option Bytes section in the device data sheet).
The OSG acts as a filter whose cross-over frequency is device dependent and provides three
basic functions:
– Filtering spikes on the oscillator lines which would result in driving the CPU at excessive fre-
quencies
– Management of the Low Frequency Auxiliary Oscillator (LFAO), (useable as low cost internal
clock source, backup clock in case of main oscillator failure or for low power consumption)
– Automatically limiting the f
INT
clock frequency as a function of supply voltage, to ensure cor-
rect operation even if the power supply drops.
The OSG function is illustrated in Figure 2. For more details on it, please refer to the Clock,
Supply and Reset section in the device data sheet.
Please note that the OSG should be used wherever possible as it provides maximum security
for the application. It should be noted however, that it can increase power consumption and re-
duce the maximum operating frequency to f
OSG
(refer to the Electrical Characteristics section
of the device data sheet).
Caution:
Care has to be taken when using the OSG, as the internal frequency is defined be-
tween a minimum and a maximum value and may vary depending on both V
DD
and tempera-
ture. For precise timing measurements, it is not recommended to use the OSG.
3/11
UPGRADING FROM ST625X/6XB TO ST625X/6XC
Figure 2. OSG Filtering Function
f
OSC>
f
OSG
f
OSC
f
OSG
f
OSC<
f
OSG
f
INT
1.1.2.1 Low Frequency Auxiliary Oscillator (LFAO)
The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to re-
duce power consumption in non timing critical routines. Secondly, it offers a fully integrated
system clock, without any external components. Lastly, it acts as a backup oscillator in case of
main oscillator failure.
This oscillator is available when the OSG option is selected in the option byte. In this case, it
automatically starts one of its periods after the first missing edge of the main oscillator, what-
ever the reason for the failure (main oscillator defective, no clock circuitry provided, main os-
cillator switched off...). See Figure 3.
Please note that the A/D converter accuracy is decreased, since the internal frequency is
below 1.2 MHz.
Figure 3. LFAO Oscillator Function
MAIN OSCILLATOR
STOPS
f
OSC
f
LFAO
f
INT
MAIN OSCILLATOR
RESTARTS
INTERNAL CLOCK DRIVEN BY LFAO
4/11
UPGRADING FROM ST625X/6XB TO ST625X/6XC
1.2 COMPATIBILITY ISSUES AND RECOMMENDATIONS
1.2.1 EEPROM
ST625X/6XC have been designed to ensure data EEPROM integrity as long as the applica-
tion designer follows the guidelines described in application note AN671.
In general, EEPROM data corruption occurs whenever the reset signal is not well controlled
when the power supply goes either up or down. This is particularly true with a slow power
supply ramp-up and/or fall time, since the device may be in a supply voltage range where its
functionality is not guaranteed. If the device is not kept in reset state during both the power up
or down sequence then the microcontroller core may start writing to the EEPROM.
To avoid EEPROM data corruption, it is therefore highly recommended to disable the
EEPROM when it is not used. Note that the EEPROM is automatically enabled on reset
(EECTL reset state = 00H).
It is also possible to prevent unwanted EEPROM write accesses by enabling the on-chip LVD
which will reset the ST6 when the voltage is out of the device operating range.
Caution:
When writing parallel data (E2PAR2 bit set), the EEPROM page must not be
changed (no access to the DRBR register is allowed).
1.2.2 I/O ports
This section gives some important recommendations on using I/O ports. These recommenda-
tions also apply to B devices but are even more important for C devices.
– Do NOT use single-bit instructions on port Data Registers.
– Configure the I/O ports following the safe I/O state switching sequence.
1.2.2.1 Instructions NOT to be used to access Port Data registers (SET, RES, INC and
DEC)
DO NOT USE SINGLE-BIT INSTRUCTIONS (SET, RES, INC and DEC) ON PORT DATA
REGISTERS IF ANY PIN OF THE PORT IS CONFIGURED IN INPUT MODE.
These instructions make an implicit read and write back of the entire register. In port input
mode, however, the data register reads from the input pins directly, and not from the data reg-
ister latches. Since data register information in input mode is used to set the characteristics of
the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed de-
pending on the state of the input pins.
As a general rule, it is better to only use single bit instructions on data registers when the
whole (8-bit) port is in output mode. In the case of inputs or of mixed inputs and outputs, it is
advisable to keep a copy of the data register in RAM. Single bit instructions may then be used
on the RAM copy, after which the whole copy register can be written to the port data register:
5/11
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
