AN2834
Application note
How to get the best ADC accuracy in STM32Fx Series and
STM32L1 Series devices
Introduction
The STM32Fx Series and STM32L1 Series microcontroller families embed up to four
advanced 12-bit ADCs (depending on the device). A self-calibration feature is provided to
enhance ADC accuracy versus environmental condition changes.
In applications involving analog-to-digital conversion, ADC accuracy has an impact on the
overall system quality and efficiency. To improve this accuracy, you need to understand the
errors associated with the ADC and the parameters affecting them.
ADC accuracy does not depend on ADC performance and features alone, it depends on the
overall application design around the ADC.
This application note aims to help understanding of ADC errors and how to enhance ADC
accuracy. It is divided into three main parts:
a simplified description of ADC internal structure to aid understanding of ADC operation
and related ADC parameters
explanations of the different types and sources of ADC errors related to the ADC design
and to external ADC parameters such as the external hardware design
recommendations on how to minimize these errors, focusing on hardware and software
methods
This document applies to the products listed in
Table 1
which are referred to as STM32x
throughout this document.
Table 1. Applicable products
Product family
–
–
–
–
–
–
STM32F0xx
STM32F1xx
STM32F2xx
STM32F3xx
STM32F4xx
STM32L1xx
Part numbers
Microcontrollers
September 2013
DocID15067 Rev 2
1/45
www.st.com
Contents
AN2834
Contents
1
ADC internal principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
SAR ADC internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
ADC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
ADC errors related to the ADC itself . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Differential linearity error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Integral linearity error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reference voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reference voltage / power supply regulation . . . . . . . . . . . . . . . . . . . . . 15
External reference voltage parameters . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog input signal noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ADC dynamic range bad match for maximum input signal amplitude . . 16
Effect of the analog signal source resistance . . . . . . . . . . . . . . . . . . . . 16
Effect of source capacitance and parasitic capacitance of the PCB . . . 17
Injection current effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature influence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I/O pin crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EMI-induced noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
ADC errors related to its environment . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
3
How to get the best ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
3.2
Reduce the effects of ADC-related ADC errors . . . . . . . . . . . . . . . . . . . . 20
Minimize ADC errors related to external environment of ADC . . . . . . . . . 20
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
Reference voltage / Power supply noise minimization . . . . . . . . . . . . . 20
Reference voltage / Power-supply regulation . . . . . . . . . . . . . . . . . . . . 22
Analog-input signal noise elimination . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Adding white noise or triangular sweep to improve resolution . . . . . . . . 22
Matching the ADC dynamic range to the maximum signal amplitude . . 23
Analog source resistance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Source frequency condition vs. source and parasitic capacitors . . . . . . 27
Temperature-effect compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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AN2834
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
Contents
Minimizing injection current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Minimizing I/O pin crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EMI-induced noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Component placement and routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Averaging samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Digital signal filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FFT for AC measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Minimizing internal CPU noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ADC input stage problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Explanation of the behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Minimizing added errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Source of described problem - ADC design . . . . . . . . . . . . . . . . . . . . . 41
3.3
Software methods to improve precision . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
High impedance source measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.1
3.4.2
3.4.3
3.4.4
4
5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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List of figures
AN2834
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Basic schematic of SAR switched-capacitor ADC (example for 10-bit ADC) . . . . . . . . . . . . 5
Sample state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Step 1: Compare with VREF/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Step 2: If MSB = 1, then compare with ¾ VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Step 2: If MSB = 0, then compare with ¼ VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Positive offset error representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Negative offset error representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Positive gain error representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Negative gain error representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Differential linearity error representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Integral linearity error representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Total unadjusted error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input signal amplitude vs. ADC dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog signal source resistance effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog input with R
AIN
, C
AIN
and C
p
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Effect of injection current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Crosstalk between I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EMI sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power supply and reference decoupling for 100- and 144-pin packages . . . . . . . . . . . . . . 21
Power supply decoupling for 36-, 48- and 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . 21
Simple quasi-triangular source using a microcontroller output . . . . . . . . . . . . . . . . . . . . . . 23
Selecting the reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Preamplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Worst case error: V
AIN
= V
REF+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Recommended values for R
AIN
and C
AIN
vs. source frequency F
AIN . . . . . . . . . . . . . . . . . . . . . . 27
Crosstalk between I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Shielding technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Separating the analog and digital layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Separating the analog and digital supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typical voltage source connection to ADC input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Noise observed on ADC input pin during ADC conversions . . . . . . . . . . . . . . . . . . . . . . . . 35
ADC simplified schematic of input stage - sample and hold circuit. . . . . . . . . . . . . . . . . . . 36
ADC input pin noise spikes from internal charge during sampling process . . . . . . . . . . . . 36
Effect of sampling time extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Charging the external capacitor with too short time between conversions . . . . . . . . . . . . . 38
Implementation of sampling switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parasitic capacitances of sampling switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parasitic current example inside ADC structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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ADC internal principle
1
1.1
ADC internal principle
SAR ADC internal structure
The ADC in STM32x microcontrollers uses the
SAR (successive approximation register)
principle, by which the conversion is performed in several steps. The number of conversion
steps is equal to the number of bits in the ADC converter. Each step is driven by the ADC
clock. Each ADC clock produces one bit from result to output. ADC internal design is a
switched-capacitor type.
The following figures (Figure
1
to
Figure 6)
explain the principle of ADC operation. The
example given below shows only the first steps of approximation but the process continues
till the LSB is reached.
Figure 1. Basic schematic of SAR switched-capacitor ADC (example for 10-bit ADC)
V
IN
Sa
V
REF
S1
C
Sb
S2
C/2
S3
C/4
S4
C/8
A
S5
C/16
S6
C/32
D PR Q
CLK
CLR
S7
C/64
S8
C/128
S9
C/256
S10
C/512
S11
C/512
ADC Data
ADC Clk
ai17097
1. Basic ADC schematic with digital output.
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