AN2691
Application note
ST10 RPD pin:
functionality during reset and Power Down mode
Introduction
RPD is a dedicated timing pin for the return-from-power-down circuit. Additionally, when this
pin is recognized low, a reset event is taken as asynchronous. This application note gives
advice on configuring the external circuitry connected to the RPD pin in order to make it
work properly.
The information contained in this document is valid for ST10F27x and ST10R27x.
March 2008
Rev 1
1/10
www.st.com
RPD functionality
AN2691
1
RPD functionality
RPD is a dual-purpose dedicated pin. This section covers its functionality.
1.1
System reset and startup
Several ST10 reset events that may occur are summarized in the following table:
Table 1.
Reset event definition
Flag
(1)
PONR
RPD
Status
Low
Low
LHWR
Synchronous long
hardware reset
Synchronous short
hardware reset
Watchdog timer reset
Software reset
SHWR
WDTR
SWR
High
High
(2)
(2)
Reset Source
Power-on reset
Asynchronous hardware
reset
Conditions
Power-on
t
RSTIN
> 500 ns
t
RSTIN
> (1032 + 12) TCL + max (4 TCL, 500 ns)
t
RSTIN
> max (4 TCL, 500 ns)
t
RSTIN
≤
(1032 + 12) TCL + max (4 TCL, 500 ns)
WDT overflow
SRST instruction execution
1. Flags can be read in the WDTCON register
2. The RPD status has no influence unless bidirectional reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the bidirectional reset on SW and WDT reset events, that is RSTIN is not activated.
Therefore, roughly, the RPD pin level distinguishes between an asynchronous (low level)
and a synchronous reset (high level). The main difference between these two kinds of reset
is that the first immediately cancels pending internal hold states and if any, it aborts all
internal/external bus cycles whereas in the synchronous reset, after RSTIN level is
detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses,
during which pending internal hold states are cancelled and the current internal access
cycle, if any, is completed. For this reason, if an asynchronous reset occurs during a read or
write phase in internal memories, the content of the memory itself could be corrupted. To
avoid this, synchronous reset usage is strongly recommended.
However, asynchronous reset must be used during the power-on of the device. Depending
on crystal or resonator frequency, the on-chip oscillator needs about 1 ms to 10 ms to
stabilize with an already stable V
DD
. The logic of the ST10 does not need a stabilized clock
signal to detect an asynchronous reset and is therefore suitable for power-on conditions.
On the contrary, the reset state machine needs a stabilized clock to operate correctly.
According to the length of pulse on RSTIN, the synchronous reset may be recognized as
long or short. Long and Short synchronous resets differ by the start-up configuration bits
latched:
–
–
Long synchronous reset latches the entire Port0 configuration, including clock
frequency selection (P0[15:13])
Short synchronous reset ignores the bits P0[15:13] and the same clock frequency
is applied.
2/10
AN2691
RPD functionality
Refer to the product documentation for a full description of the reset mechanism.
The RSTIN pin is an input of the device that can be configured as an output that shows a
low level during the internal reset condition. This is called bidirectional reset and is enabled
by setting the BDRSTEN bit in the SYSCON register.
When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal
for the duration of the internal reset sequence (synchronous/asynchronous hardware,
synchronous software and synchronous watchdog timer resets). At the end of the internal
reset sequence (1024 TCL) the pull-down is released.
The figure below shows a simplified reset circuitry scheme. Please refer to the product user
manual for more details and timings related to system reset.
Figure 1.
Internal (simplified) reset circuitry
EINIT instruction
Clr
Q
Set
RSTOUT
Reset state
machine
Clock
V
DD
Internal
reset
signal
Trigger
Clr
SRST instruction
watchdog overflow
RSTIN
BDRSTEN
Reset sequence
(512 CPU clock cycles)
V
DD
Asynchronous
reset
RPD
From/to exit
powerdown
circuit
Weak pull-down
(–200 µA)
3/10
RPD functionality
AN2691
1.2
Power down
To reduce power consumption, the microcontroller can be switched to Power Down mode.
Clocking of all internal blocks is stopped, the contents of the internal RAM, however, are
preserved through the voltage supplied via the V
DD
pins (and on-chip voltage regulator).
The ST10 provides two different operating Power Down modes:
●
●
Protected Power Down mode
Interruptible Power Down mode
The Power Down operating mode is selected by the bit PWDCFG in the SYSCON register.
In the first case, the Power Down mode can only be entered if the NMI (Non Maskable
Interrupt) pin is externally pulled low while the PWRDN instruction is executed and the only
way to exit the Power Down mode is with an external hardware reset.
In the second case, the Power Down mode can be entered if enabled Fast External Interrupt
pins (EXxIN pins, alternate functions of Port 2 pins, with x = 7...0) are at their inactive level.
This inactive level is configured with the EXIxES bit field in the EXICON register, as follows:
EXICON (F1C0H / E0H)
15
14
13
12
11
10
9
8
ESFR
7
6
5
4
3
Reset value: 0000H
2
1
0
EXI7ES
RW
EXI6ES
RW
EXI5ES
RW
EXI4ES
RW
EXI3ES
RW
EXI2ES
RW
EXI1ES
RW
EXI0ES
RW
EXIxES External Interrupt x Edge Selection Field (x=7...0)
(x=7...0) ‘00’: Fast external interrupts disabled: Standard mode.
EXxIN pin not taken into account for entering/exiting Power Down mode.
‘01’: Interrupt on positive edge (rising).
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred to as ‘high’ active level)
‘10’: Interrupt on negative edge (falling).
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred to as ‘low’ active level)
‘11’: Interrupt on any edge (rising or falling).
Always enter Power Down mode, exit if EXxIN level changed.
Interruptible Power Down mode can be exited by asserting either RSTIN or one of the
enabled EXxIN pins (Fast External Interrupt).
4/10
AN2691
Figure 2.
Simplified power down exit circuitry
V
DD
D
Q1
Enter
Power Down
cd Q
exit_pwrd
Pull-up
Q
stop PLL
stop oscillator
V
DD
RPD functionality
RPD
Weak pull-down
(–200 µA)
External
interrupt
Reset
V
DD
D
Q2
cd Q
system clock
Q
en_clk_n
CPU and peripherals clocks
5/10
FPGA/CPLD
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