AN2945
Application note
STM8S and STM32™ MCUs: a consistent 8/32-bit product line
for painless migration
Introduction
Following the market launch of the award winning STM32™ microcontroller,
STMicroelectronics completes the renewal of its microcontroller product line with the
announcement of the STM8S family. Significant effort has been made to rationalize the
MCU portfolio, in particular by capitalizing on common peripherals and software tools with
the aim to easing product migration.
The cost, in terms of both time and money, of maintaining a development team to design in
a new MCU family is a major criterion when selecting a microcontroller supplier. It is
therefore an advantage to make this kind of non-recurring investment if it applies to a broad
range of MCUs. With an MCU product line ranging from 20 to 144 pins, and memory sizes
from 2 to 512 Kbytes, the 8-bit STM8S and 32-bit STM32 families bring a lot of flexibility
when building a product portfolio. Should an 8-bit application run out of MIPS, there is an
upgrade path to the STM32 family. Conversely, if you wish to cut costs on a 32-bit platform,
it is relatively simple to switch to the STM8 family.
This document presents the similarities and common features of the STM8S and STM32
product lines, with a view of helping migration from one family to the other.
July 2009
Doc ID 15468 Rev 1
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www.st.com
Contents
AN2945
Contents
1
2
3
Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
6
Software library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
STM8 and STM32: core comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
STM32 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM8 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Peripherals shared between STM8 and STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STM8S/STM32 clock source characteristics (indicative data) . . . . . . . . . . . . . . . . . . . . . . 11
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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List of figures
AN2945
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Digital peripheral’s internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM8S and STM32 reset circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM8S code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32 code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Core
1
Core
The STM8™ CPU is a proprietary architecture that maintains the legacy of the previous ST7
core while being a breakthrough in terms of 8-bit CPU efficiency and code density. The
STM32 is built around the industry standard ARM
®
Cortex™-M3 32-bit core and benefits
from the complete ecosystem of development tools and software solutions associated with
ARM processors. Although they may be perceived as radically different, these two
processors indeed share many architectural similarities summarized in
Table 1.
Table 1.
STM8 and STM32: core comparison
STM8
Data path
Drhystone MIPS (0WS)
Architecture
Pipeline
Instruction set
Program bus data width
Prefetch buffer
Average instruction size
Interrupt type
Latency
Low power modes
Debug interface
8-bit
0.29 DMIPS
Harvard
Yes, three-stage
CISC
32-bit
Yes, 2 × 32-bit, internal
2 bytes
Vectorized
9 cycles, tail chaining supported
32-bit
1.22 DMIPS
Harvard
Yes, three-stage
RISC
32-bit
Yes, 2 × 64-bit, in memory interface
2 bytes
Vectorized
12 cycles, tail chaining supported
Cortex-M3
Slow, Wait for Event or interrupts, Slow, Sleep (Wait for event or
Halt, Halt on exit
interrupt), Sleep on exit, Deep sleep
1-wire (SWIM)
2-wires or legacy JTAG
Both are based on the Harvard architecture. They have 3-stage pipelined execution that
minimizes the execution time, a clock speed up to 24 MHz for the STM8S and up to 72 MHz
for the STM32 family.
They are devised to be highly energy efficient, with several low power modes, and they
benefit from memory interfaces wider than the average instruction length (32- and 64-bit
wide busses, respectively). This minimizes the number of accesses to the memory bus and
thus the consumption related to address bus toggling and non-volatile memory read
accesses. Interrupt tail chaining and the Halt/Sleep on exit modes also help avoiding
unnecessary stack accesses.
Finally, in terms of code density, both have excellent results, owing to the 8-bit CISC
instruction set for the STM8S family and, to the 16-bit Thumb-2 mode introduced by the
Cortex core for the STM32 family.
This short comparison demonstrates that both processors are state-of-the-art in terms of
micro-architectural features. The STM8 is at the level of legacy of 16-bit processors, and the
Cortex-M3 meets the requirements of applications currently using 32-bit down to mid/high-
end 16-bit MCUs. The combination of the STM8 and STM32 therefore establishes a
performance continuum, which is now also supported at tool levels by a third party offering a
unified development platform for both product lines.
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