LTC1403/LTC1403A
Serial 12-Bit/14-Bit, 2.8Msps
Sampling ADCs with Shutdown
FEATURES
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DESCRIPTION
The LTC
®
1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-
rial ADCs with differential inputs. The devices draw only
4.7mA from a single 3V supply and come in a tiny 10-lead
MS package. A Sleep shutdown feature lowers power
consumption to 10μW. The combination of speed, low
power and tiny package makes the LTC1403/LTC1403A
suitable for high speed, portable applications.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differentially.
The absolute voltage swing for +A
IN
and –A
IN
extends from
ground to the supply voltage.
The serial interface sends out the conversion results during
the 16 clock cycles following CONV↑ for compatibility with
standard serial interfaces. If two additional clock cycles
for acquisition time are allowed after the data stream in
between conversions, the full sampling rate of 2.8Msps
can be achieved with a 50.4MHz clock.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2.8Msps Conversion Rate
Low Power Dissipation: 14mW
3V Single Supply Operation
–40°C to 125°C Guaranteed Operation
2.5V Internal Bandgap Reference can be Overdriven
3-Wire Serial Interface
Sleep (10μW) Shutdown Mode
Nap (3mW) Shutdown Mode
80dB Common Mode Rejection
0V to 2.5V Unipolar Input Range
Tiny 10-Lead MS Package
APPLICATIONS
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Automotive
Communications
Data Acquisition Systems
Uninterrupted Power Supplies
Multiphase Motor Control
Multiplexed Data Acquisition
BLOCK DIAGRAM
10μF
3V
2nd, 3rd and SFDR vs
Input Frequency
V
DD
14-BIT LATCH
THREE-
STATE
SERIAL
OUTPUT
PORT
14
–44
–50
LTC1403A
A
IN
+
7
THD, 2nd, SFDR, 3rd (dB)
1
+
S&H
14-BIT ADC
–56
–62
–68
–74
–80
–86
–92
3rd
THD
2nd, SFDR
8
SDO
A
IN–
2
–
V
REF
2.5V
REFERENCE
3
10μF
4
10
TIMING
LOGIC
9
6
11
EXPOSED PAD
CONV
GND
5
SCK
1403A TA01
–98
–104
0.1
1
10
FREQUENCY (MHz)
100
1403A TA02
1403fb
1
LTC1403/LTC1403A
ABSOLUTE MAXIMUM RATINGS
(Note 1, 2,)
PACKAGE/ORDER INFORMATION
TOP VIEW
A
IN+
1
A
IN–
2
V
REF
3
GND 4
GND 5
10
9
8
7
6
CONV
SCK
SDO
V
DD
GND
11
Supply Voltage (V
DD
) ..................................................4V
Analog Input Voltage
(Note 3) ....................................–0.3V to (V
DD
+ 0.3V)
Digital Input Voltage......................–0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ...................–0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC1403C/LTC1403AC ............................. 0°C to 70°C
LTC1403I/LTC1403AI ........................... –40°C to 85°C
LTC1403H/LTC1403AH ...................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
MSE PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 150°C,
θ
JA
= 40°C/W
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC1403CMSE
LTC1403IMSE
LTC1403HMSE
LTC1403ACMSE
LTC1403AIMSE
LTC1403AHMSE
MSE PART MARKING
LTBDN
LTBDP
LTBDP
LTADF
LTAFD
LTAFD
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CONVERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
Gain Error
Gain Tempco
(Notes 4, 5, 18)
(Notes 4, 18)
(Note 4, 18)
Internal Reference (Note 4)
External Reference
CONDITIONS
●
●
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With internal reference. V
DD
= 3V
LTC1403
12
–2
±0.25
±1
±5
±15
±1
2
10
30
12
–2
–20
–40
±0.25
±2
±5
±15
±1
2
20
40
LTC1403H
14
–4
–20
–60
±0.5
±2
±10
±15
±1
4
20
60
LTC1403A
LTC1403AH
14
–4
–30
–80
±0.5
±2
±10
±15
±1
4
30
80
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
Bits
LSB
LSB
LSB
ppm/°C
ppm/°C
●
–10
●
–30
ANALOG INPUT
SYMBOL
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
CMRR
PARAMETER
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. V
DD
= 3V
CONDITIONS
2.7V ≤ V
DD
≤ 3.3V
●
MIN
TYP
0 to 2.5
0 to V
DD
MAX
UNITS
V
V
Analog Differential Input Range (Notes 3, 9)
Analog Common Mode + Differential Input Range (Note 10)
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
●
1
13
39
1
0.3
μA
pF
ns
ns
ps
dB
dB
1403fb
(Note 6)
●
f
IN
= 1MHz, V
IN
= 0V to 3V
f
IN
= 100MHz, V
IN
= 0V to 3V
–60
–15
2
LTC1403/LTC1403A
DYNAMIC ACCURACY
SYMBOL
SINAD
PARAMETER
Signal-to-Noise Plus
Distortion Ratio
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. V
DD
= 3V
CONDITIONS
100kHz Input Signal
1.4MHz Input Signal
1.4MHz Input Signal (H Grade)
100kHz Input Signal, External V
REF
= 3.3V,
V
DD
≥ 3.3V
750kHz Input Signal, External V
REF
= 3.3V,
V
DD
≥ 3.3V
100kHz First 5 Harmonics
1.4MHz First 5 Harmonics
100kHz Input Signal
1.4MHz Input Signal
1.25V to 2.5V 1.25MHz into A
IN+
, 0V to 1.25V,
1.2MHz into A
IN–
V
REF
= 2.5V (Note 18)
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(Note 15)
S/(N + D) ≥ 68dB
LTC1403/LTC1403H
MIN
●
●
LTC1403A/LTC1403AH
MIN
70
69
TYP
73.5
73.5
73.0
76.3
76.3
–90
–86
–90
–86
–82
1
50
5
MAX
TYP
70.5
70.5
70.5
72
72
–87
–83
–87
–83
–82
0.25
50
5
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LSB
RMS
MHz
MHz
68
67
THD
SFDR
IMD
Total Harmonic
Distortion
Spurious Free
Dynamic Range
Intermodulation
Distortion
Code-to-Code
Transition Noise
Full Power Bandwidth
Full Linear Bandwidth
●
–76
–78
INTERNAL REFERENCE CHHARACTERISTICS
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V
CONDITIONS
I
OUT
= 0
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
Load Current = 0.5mA
PARAMETER
V
REF
Output Voltage
V
REF
Output Tempco
V
REF
Line Regulation
V
REF
Output Resistance
V
REF
Settling Time
MIN
TYP
2.5
15
600
0.2
2
MAX
UNITS
V
ppm//°C
μV/V
Ω
ms
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
OUT
= 0V, V
DD
= 3V
V
OUT
= V
DD
= 3V
V
DD
= 3V, I
OUT
= –200μA
V
DD
= 2.7V, I
OUT
= 160μA
V
DD
= 2.7V, I
OUT
= 1.6mA
V
OUT
= 0V to V
DD
CONDITIONS
V
DD
= 3.3V
V
DD
= 2.7V
V
IN
= 0V to V
DD
The
●
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V
MIN
●
●
●
TYP
MAX
0.6
±10
UNITS
V
V
μA
pF
V
V
V
μA
pF
mA
mA
1403fb
2.4
5
●
●
●
2.5
2.9
0.05
0.10
1
20
15
0.4
±10
3
LTC1403/LTC1403A
POWER REQUIREMENTS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 17)
SYMBOL
V
DD
I
DD
PARAMETER
Supply Voltage
Positive Supply Voltage
CONDITIONS
Active Mode
Active Mode (LTC1403H, LTC1403AH)
Nap Mode
Nap Mode (LTC1403H, LTC1403AH)
Sleep Mode (LTC1403, LTC1403H)
Sleep Mode (LTC1403A, LTC1403AH)
Active Mode with SCK in Fixed State (Hi or Lo)
●
●
●
●
MIN
2.7
TYP
4.7
5.2
1.1
1.2
2
2
12
MAX
3.6
7
8
1.5
1.8
15
10
UNITS
V
mA
mA
mA
mA
μA
μA
mW
P
D
Power Dissipation
TIMING CHARACTERISTICS
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
1
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
12
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V
CONDITIONS
●
●
SYMBOL
PARAMETER
f
SAMPLE(MAX)
Maximum Sampling Frequency per Channel (Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum Positive or Negative SCLK Pulse Width
CONV to SCK Setup Time
Nearest SCK Edge Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK to Sample Mode
CONV to Hold Mode
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 13
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
MIN
2.8
19.8
16
2
3
0
4
4
1.2
45
8
6
2
TYP
MAX
357
10000
UNITS
MHz
ns
ns
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Notes 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
●
18
2
ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device reliability
and lifetime.
Note 2:
All voltage values are with respect to GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and full-scale specifications are measured for a single-ended
A
IN+
input with A
IN–
grounded and using the internal 2.5V reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through the
actual endpoints of a transfer curve. The deviation is measured from the
center of quantization band.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference between
A
IN+
and A
IN–
.
Note 9:
The absolute voltage at A
IN+
and A
IN–
must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when running
the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming out
into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.
Note 17:
V
DD
= 3V, f
SAMPLE
= 2.8Msps.
Note 18:
The LTC1403A is measured and specified with 14-bit Resolution
(1LSB = 152μV) and the LTC1403 is measured and specified with 12-bit
Resolution (1LSB = 610μV).
1403fb
4
LTC1403/LTC1403A
TYPICAL PERFORMANCE CHARACTERISTICS
ENOBs and SINAD
vs Input Frequency
12.0
11.5
11.0
ENOBs (BITS)
10.5
10.0
9.5
9.0
8.5
8.0
0.1
1
10
FREQUENCY (MHz)
74
71
68
65
62
59
56
53
50
100
1403A G01
T
A
= 25°C, V
DD
= 3V (LTC1403A)
SFDR vs Input Frequency
104
98
THD, 2nd and 3rd vs Input
Frequency
–44
–50
–56
THD, 2nd, 3rd (dB)
–62
–68
–74
–80
–86
–92
–98
–104
0.1
1
10
FREQUENCY (MHz)
100
1403A G02
THD
2nd
SFDR (dB)
92
86
80
74
68
62
56
50
44
0.1
1
10
FREQUENCY (MHz)
100
1403A G17
SINAD (dB)
3rd
SNR vs Input Frequency
74
71
68
MAGNITUDE (dB)
SNR (dB)
65
62
59
56
53
50
0.1
1
10
FREQUENCY (MHz)
100
1403A G03
98kHz Sine Wave 4096 Point
FFT Plot
0
–10
–20
–30
MAGNITUDE (dB)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
350k
700k
1.05M
FREQUENCY (Hz)
1.4M
1403A G04
1.3MHz Sine Wave 4096 Point
FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
350k
700k
1.05M
FREQUENCY (Hz)
1.4M
1403A G05
2.8Msps
2.8Msps
1.4MHz Input Summed with
1.56MHz Input IMD 4096 Point
FFT Plot
0
–10
–20
–30
MAGNITUDE (dB)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
350k
700k
1.05M
FREQUENCY (Hz)
1.4M
1403A G06
Differential Linearity
vs Output Code
1.0
0.8
4
3
INTEGRAL LINEARITY (LSB)
2
1
0
–1
–2
–3
–4
0
4096
8192
12288
OUTPUT CODE
16383
1403A G13
Integral Linearity
vs Output Code
2.8Msps
DIFFERENTIAL LINEARITY (LSB)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
12288
OUTPUT CODE
16383
1403A G14
1403fb
5
FPGA/CPLD
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