TS19450
Taiwan Semiconductor
AC/DC WLED Driver with External MOSFET
Universal High Brightness
DESCRIPTION
The TS19450 is an open loop, current mode control
LED driver IC. It can be programmed to operate in
either a constant frequency or constant off-time mode.
It includes an 8V~450V linear regulator which allows it
to work from a wide range of input voltages without the
need for an external low voltage supply. The TS19450
includes a PWM dimming input that can accept an
external control signal with a duty ratio of 0~100% and
a frequency of up to a few kHz. It also includes a
0~250mV linear dimming input which can be used for
linear dimming of the LED current.
The TS19450 is ideally suited for buck LED drivers.
Since it operates in open loop current mode control,
the controller achieves good output current
regulation without the need for any loop
compensation. PWM dimming response is limited
only by the rate of rise and fall of the inductor
current, enabling very fast rise and fall times. The
TS19450 requires only free external components
(apart from the power stage) to produce a controlled
LED current making it an ideal solution for low cost
LED drivers.
SOP-8
Pin Definition:
1. V
IN
8. RT
2. CS
7. LD
3. GND
6. V
DD
4. Gate
5. PWMD
Notes:
Moisture sensitivity level: level 3. Per J-STD-020
FEATURES
●
●
●
●
●
●
●
●
●
●
●
●
Switch mode controller for single switch LED
drivers
Open loop peak current controller
Internal 8V~450V linear regulator
Constant frequency or constant off-time operation
Linear and PWM dimming capability
Requires few external components for operation
APPLICATION
DC/DC or AC/DC LED driver applications
RGB backlighting LED driver
Back lighting of flat panel displays
General purpose constant current source
Signage and decorative LED lighting
Charger
TYPICAL APPLICATION CIRCUIT
Document Number: DS_P0000187
1
Version: B15
TS19450
Taiwan Semiconductor
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise specified)
(Note 1)
PARAMETER
Input Voltage Range
Internal Regulated Voltage
CS, LD, PWMD, Gate, RT to GND
Continuous Power Dissipation
(Note 2)
Storage Temperature Range
Junction Temperature Range
P
D
T
A
T
J
(Note 3)
SYMBOL
V
IN
to GND
V
DD
to GND
LIMIT
-0.5 ~ +470
13.5
-0.3 ~ (V
DD
+0.3)
630
-65 to +150
-40 to +150
UNIT
V
V
V
mW
o
o
C
C
THERMAL PERFORMANCE
PARAMETER
SYMBOL
R
θJA
LIMIT
128
UNIT
o
Thermal Resistance – Junction to Ambient
C/W
ELECTRICAL SPECIFICATIONS
(T
A
= 25
o
C, V
IN
= 12V, unless otherwise noted)
(Note 4)
PARAMETER
Input
DC Input Voltage Range
Shut-down Mode Supply Current
Internal Regulator
V
IN
=8V, I
DD(EXT)
=0,
Internally Regulated Voltage
V
DD
500pF at Gate,
R
T
=226kΩ
V
IN
=8~450V, I
DD(EXT)
=0
Line Regulation of V
DD
∆V
DDLine
500pF at Gate,
R
T
=226kΩ
I
DD(EXT)
= 0 ~ 1mA
500pF at Gate,
R
T
=226kΩ, PWMD=V
DD
V
IN
rising
V
IN
falling
V
IN
=8V~100V
0
--
1.0
V
7.25
7.5
7.75
V
V
INDC
I
INSD
DC input voltage
Pin PWMD to GND
8.0
--
--
0.5
450
1.0
V
mA
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
Load Regulation of V
DD
Undervoltage Lockout Threshold
Undervoltage Lockout
Hysteresis
VDD current available for
external circuitry
(Note 5)
Dimming
PWMD Input Low Voltage
PWMD Input High Voltage
PWMD Pull-down resistance at
PWMD
Linear Dimming pin Voltage
∆V
DDLoad
UVLO
∆UVLO
V
DD (EXT)
0
6.45
--
--
--
6.7
500
--
100
6.95
--
1.0
mV
V
mV
mA
V
ENL
V
ENH
R
EN
V
LD
V
IN
=8V~450V
V
IN
=8V~450V
V
PWMD
=5V
V
IN
=12V
--
2.4
50
0
--
--
100
--
1.0
--
150
250
V
V
kΩ
mV
Document Number: DS_P0000187
2
Version: B15
TS19450
Taiwan Semiconductor
ELECTRICAL SPECIFICATIONS
(T
A
= 25
o
C, V
IN
= 12V, unless otherwise noted)
(Note 4)
PARAMETER
Current Sense Comparator
Current Sense Pull-in Threshold
Voltage
Offset Voltage for LD
Comparator
Current Sense Blanking Interval
Delay to Output
Oscillator
Oscillator Frequency
Max. Oscillator PWM Duty Cycle
Gate Driver
Gate Sourcing Current
Gate Sinking Current
Gate High Output Voltage
Gate Low Output Voltage
Gate Output Rise Time
Gate Output Fall Time
I
SOURCE
I
SINK
V
GATE(HI)
V
GATE(LO)
T
RISE
T
FALL
V
GATE
=0V, V
DD
=7.5V
V
GATE
=V
DD
, V
DD
=7.5V
I
OUT
=-10mA
I
OUT
=10mA
C
GATE
=500pF, 10%~90%
V
GATE
C
GATE
=500pF, 90%~10%
V
GATE
165
165
V
DD
-
0.3
0
--
--
--
--
--
--
30
30
--
--
V
DD
0.3
50
50
mA
mA
V
V
ns
ns
f
OSC
D
MAX
R
T
=1MΩ
R
T
=223kΩ
F=25kHz at Gate, CS to
GND
20
80
--
25
100
--
30
120
100
%
kHz
V
CSTH
V
OFFSET
T
BLANK
T
DELAY
V
LD
=V
DD
, V
CS
=0.55V
LD
V
IN
=12V, V
LD
=0.15V,
V
CS
=0~0.22V after
T
BLANK
-40ºC < T
A
< +85ºC
T
A
< +125ºC
225
213
-12
150
--
250
250
--
215
--
275
287
12
280
300
mV
mV
ns
ns
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
Note:
1.
Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These
are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may remain possibility to affect device reliability.
2.
Limited by package power dissipation, whichever is lower.
3. Thermal Resistance is specified with the component mounted on a low effective thermal conductivity test board
in free air at T
A
=25°C.
4.
Denotes the specifications which apply over the full operating ambient temperature range of -40ºC<T
A
<+125ºC.
5.
V
DD
load current external to the TS19450.
Document Number: DS_P0000187
3
Version: B15
TS19450
Taiwan Semiconductor
ORDERING INFORMATION
PART NO.
TS19450CS RLG
PACKAGE
SOP-8
PACKING
2,500pcs / 13” Reel
Note:
1. Compliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/EC.
2. Halogen-free according to IEC 61249-2-21 definition.
Document Number: DS_P0000187
4
Version: B15
TS19450
Taiwan Semiconductor
FUNCTION BLOCK DIAGRAM
PIN DESCRIPTION
PIN NO.
1
2
NAME
VIN
CS
FUNCTION
This pin is the input of 8V~450V linear regulator
This pin is the current sense pin used to sense the MOSFET current by means
of an external sense resistor. When this pin exceeds the low of either the
internal 250mV or the voltage at the LD pin, the GATE output goes low
Ground return for all internal circuitry. This pin must be electrically connected
to the ground of the power train.
This pin is the output GATE driver for an external N-CH Power MOSFET
This is the PWM dimming input of the IC. When this pin is pulled to GND, the
Gate Driver is turned off. When the pin is pulled high, the GATE driver
operates normally.
This is the power supply pin for all internal circuits.
It must be bypassed with a low ESR capacitor to GND (≥0.1µF)
This pin is the linear dimming input and sets the current sense threshold as
long as the voltage at the pin is less than 250mV (typ.)
This pin sets the oscillator frequency. When a resistor is connected between
RT and GND, the IC operates in constant frequency mode. When the resistor
is connected between RT and GATE, the IC operates in constant off-time
mode.
3
4
5
GND
GATE
PWMD
6
7
VDD
LD
8
RT
Document Number: DS_P0000187
5
Version: B15
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
