integrated, fixed gain, differential ADC drivers. The low
noise amplifiers are suitable for single-ended drive and
pulse train signals such as imaging applications. Each
channel includes a lowpass filter between the driver out-
put and ADC input.
DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1.2LSB
RMS
.
The digital outputs are serial LVDS and each channel out-
puts two bits at a time (2-lane mode). At lower sampling
rates there is a one bit option (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
4-Channel Simultaneous Sampling ADC with
Integrated, Fixed Gain, Differential Drivers
68.3dB SNR
78dB SFDR
Low Power: 1.27W Total, 318mW per Channel
1.8V ADC Core and 3.3V Analog Input Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Shutdown and Nap Modes
11.25mm × 15mm BGA Package
applicaTions
n
n
n
n
Industrial Imaging
Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
Single-Ended Sensor Digitization
3.3V
V
CC
1.8V
V
DD
PIPELINE
ADC
IMAGE
SENSOR
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
V
REF
INTERNAL
REFERENCE & SUPPLY
BYPASS CAPACITORS
14
1.8V
OV
DD
LTM9012
LTM9012, 125Msps, 70MHz FFT
0
–10
–20
AMPLITUDE (dBFS)
–30
–40
–50
–60
–70
–80
–90
–100
FR
+
14
•
•
•
DATA
CHANNEL 1
SERIALIZER
ENCODER
AND
CHANNEL 2
LVDS
DRIVERS
CHANNEL 3
CHANNEL 4
FR
–
PLL
+
FPGA
14
14
–110
–120
0
5 10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (MHz)
9012 TA01b
DCO
+
ENC
–
DCO
–
SCK SDI SDO
CS
PAR/SER ENC
ENCODE CLOCK
9012 TA01a
9012f
1
LTM9012
absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTion
TOP VIEW
1
A
B
V
CC3
SHDN3
VCC2
SHDN2
Supply Voltages
V
DD
, OV
DD
................................................ –0.3V to 2V
V
CC
........................................................ –0.3V to 5.5V
Analog Input Voltage (CHn
+
, CHn
–
,
SHDNn
)
(Note 3) .......................................................–0.3V to V
CC
Analog Input Voltage (PAR/SER, SENSE)
(Note 4)........................................ –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK)
(Note 5)..................................................... –0.3V to 3.9V
SDO (Note 5)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTM9012C ............................................... 0°C to 70°C
LTM9012I.............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
2
3
4
5
6
7
8
9
10
11
12
13
CH4+ CH4–
CH3+ CH3–
CH2+ CH2–
CH1+ CH1–
C
D
E
F
SHDN4
V
CC4
SHDN1
G
H
J
K
L
VCC1
SDI
SENSE
M
N
P
Q
R
S
D3A– D3A+ FR–
FR+
OV
DD
DCO– DCO+ D2B– D2B+
D2A– D2A+ D1B– D1B+
ALL ELSE = GND
VDD
SDO
PAR/SER
REF
D1A+
D1A–
V
DD
ENC+
ENC –
CS
D4B –
D4B+
D4A– D4A+ D3B– D3B+ SCK
BGA PACKAGE
221-LEAD (15mm × 11.25mm)
T
JMAX
= 125°C,
θ
JA
= 16.5°C/W,
θ
JCtop
= 15°C/W,
θ
JCbottom
= 6.3°C/W,
θ
JBOARD
= 10.4°C/W
θ
VALUES DETERMINED PER JESD 51-9
WEIGHT = 1.07g
orDer inForMaTion
LEAD FREE FINISH
LTM9012CY-AB#PBF
LTM9012IY-AB#PBF
TRAY
LTM9012CY-AB#PBF
LTM9012IY-AB#PBF
PART MARKING*
LTM9012YAB
LTM9012YAB
PACKAGE DESCRIPTION
221-Lead (15mm
×
11.25mm) Plastic BGA
221-Lead (15mm
×
11.25mm) Plastic BGA
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to:
http://www.linear.com/packaging/
9012f
2
LTM9012
converTer characTerisTics
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
External Reference
Internal Reference
External Reference
External Reference
Differential Analog Input (Note 7)
Differential Analog Input
(Note 8)
Internal Reference
External Reference
CONDITIONS
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 6)
MIN
14
–5
–0.9
–37
–3.6
±1.2
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
5
0.9
37
3.0
TYP
MAX
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
analog inpuT
SYMBOL
V
IN
V
IN(CM)
V
SENSE
R
IN
I
IN(P/S)
I
IN(SENSE)
t
AP
t
JITTER
CMRR
BW-3dB
PARAMETER
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 6)
CONDITIONS
LTM9012-AB
Differential Analog Input (Note 9)
l
l
MIN
TYP
0.2
0 to 1.5
MAX
UNITS
V
P-P
V
Differential Analog Input Range (CH
+
– CH
–
)
at –1dBFS
Analog Input Common Mode (CH
+
+ CH
–
)/2
Differential Input Resistance
Input Leakage Current
Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
3dB Corner of Internal Lowpass Filter
External Voltage Reference Applied to SENSE External Reference Mode
LTM9012-AB
0 < PAR/SER < V
DD
0.625V < SENSE < 1.3V
0.625
–3
–6
1.250
100
1.300
3
6
V
Ω
µA
µA
ns
ps
RMS
dB
MHz
l
l
0
0.15
90
90
DynaMic accuracy
SYMBOL
SNR
SFDR
PARAMETER
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. (Note 6)
CONDITIONS
70MHz Input
70MHz Input
70MHz Input
70MHz Input
10MHz (Note 12)
10MHz (Note 12)
l
l
l
l
MIN
66.5
66.9
76.9
64.7
TYP
68.3
78
86
66.7
70
90
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
Spurious Free Dynamic Range
2nd or 3rd Harmonic
Spurious Free Dynamic Range
4th Harmonic or Higher
S/N+D
Signal-to-Noise Plus Distortion Ratio
Crosstalk, Near Channel
Crosstalk, Far Channel
9012f
3
LTM9012
inTernal reFerence characTerisTics
PARAMETER
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400μA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
CONDITIONS
I
OUT
= 0
full operating temperature range, otherwise specifications are at T
A
= 25°C.
The
l
denotes the specifications which apply over the
MIN
1.225
TYP
1.250
±25
7
0.6
MAX
1.275
UNITS
V
ppm/°C
Ω
mV/V
DigiTal inpuTs anD ouTpuTs
SYMBOL
PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OH
I
OH
C
OUT
V
IH
V
IL
R
SHDN
V
OD
V
OS
R
TERM
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
High Level Input Voltage
Low Level Input Voltage
SHDN
Pull-Up Resistor
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 6)
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 9)
Internally Set
Externally Set (Note 9)
ENC
+
, ENC
–
to GND
(See Figure 3)
l
l
l
0.2
1.1
0.2
10
3.5
1.2
1.6
3.6
V
V
V
V
kΩ
pF
V
V
V
kΩ
pF
V
0.6
V
µA
pF
Ω
10
3
µA
pF
1.4
210
454
250
1.375
1.375
V
V
kΩ
mV
mV
V
V
Ω
9012f
Single-Ended Encode Mode (ENC
–
Tied to GND)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 4)
1.26
0.54
0 to 3.6
30
3.5
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
l
l
l
Digital Inputs (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
1.3
–10
3
V
DD
= 1.8V, SDO = 0V
SDO = 0V to 3.6V
l
10
SDO Output (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
200
–10
Digital Input (SHDN)
V
CC
= 3.3V
V
CC
= 3.3V
V
SHDN
= 0V to 0.5V
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
0.97
0.6
90
247
125
1.125
1.125
0.95
150
350
175
1.250
1.250
100
Digital Data Outputs
l
l
l
l
4
LTM9012
power requireMenTs
SYMBOL
V
DD
OV
DD
V
CC
I
VDD
I
OVDD
I
VCC
P
DISS
P
SLEEP
P
NAP
P
DIFFCLK
Power Decrease with Single-Ended
Encode Mode Enabled
PARAMETER
ADC Supply Voltage
ADC Output Supply Voltage
Amplifier Supply Voltage
ADC Supply Current
ADC Output Supply Current
Amplifier Supply Current
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 6)
CONDITIONS
(Note 10)
(Note 10)
(Note 10)
Sine Wave Input
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
l
l
l
l
l
l
l
l
MIN
1.7
1.7
2.7
TYP
1.8
1.8
3.3
298
27
49
208
1271
1311
3
85
20
MAX
1.9
1.9
3.6
320
31
54
224
1473
1517
UNITS
V
V
V
mA
mA
mA
mA
mW
mW
mW
mW
mW
TiMing characTerisTics
SYMBOL
f
S
t
ENCL
t
ENCH
t
AP
PARAMETER
Sampling Frequency
ENC Low Time (Note 9)
ENC High Time (Note 9)
Sample-and-Hold
Acquisition Delay Time
Serial Data Bit Period
CONDITIONS
The
l
denotes the specifications which apply over the full operating temperature
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
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