RFFC2071/2072
2.7GHz RF SYNTHESIZER/VCO WITH
INTEGRATED RF MIXER
Package: QFN, 32-Pin, 5mm x 5mm
RFFC2071
RFFC2072
Features
85MHz to 2700MHz LO
Frequency Range
Fractional-N Synthesizer with
Very Low Spurious Levels
Typical Step Size 1.5Hz
Fully Integrated Low Phase Noise
VCO and LO Buffers
Integrated Phase Noise
0.18°rms at 1GHz
High Linearity RF Mixer(s)
30MHz to 2700MHz Mixer
Frequency Range
Input IP3 +23dBm
Mixer Bias Adjustable for Low
Power Operation
Full Duplex Mode (RFFC2071)
2.7V to 3.3V Power Supply
Low Current Consumption
3- or 4-Wire Serial Interface
Phase
det.
Synth
Phase
det.
Synth
Ref.
divider
Ref.
divider
Functional Block Diagram
Product Description
The RFFC2071 and RFFC2072 are re-configurable frequency conversion devices
with integrated fractional-N phased locked loop (PLL) synthesizer, voltage con-
trolled oscillator (VCO) and either one or two high linearity mixers. The fractional-N
synthesizer takes advantage of an advanced sigma-delta modulator that delivers
ultra-fine step sizes and low spurious products. The PLL/VCO engine combined with
an external loop filter allows the user to generate local oscillator (LO) signals from
85MHz to 2700MHz. The LO signal is buffered and routed to the integrated RF mix-
ers which are used to up/down-convert frequencies ranging from 30MHz to
2700MHz. The mixer bias current is programmable and can be reduced for applica-
tions requiring lower power consumption. Both devices can be configured to work
as signal sources by bypassing the integrated mixers. Device programming is
achieved via a simple 3-wire serial interface. In addition, a unique programming
mode allows up to four devices to be controlled from a common serial bus. This
eliminates the need for separate chip-select control lines between each device and
the host controller. Up to six general purpose outputs are provided, which can be
used to access internal signals (the LOCK signal, for example) or to control front
end components. Both devices operate with a 2.7V to 3.3V power supply.
Applications
CATV Head-Ends
Digital TV Repeaters
Multi-Dwelling Units
Diversity Receivers
Software Defined Radios
Frequency Band Shifters
Point-to-Point Radios
Cellular Repeaters
WiMax/LTE Infrastructure
Cellular Jammers
Satellite Communications
VHF/UHF Radios
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
BiFET HBT
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2012, RF Micro Devices, Inc.
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
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RFFC2071/2072
Absolute Maximum Ratings
Parameter
Supply Voltage (V
DD
)
Input Voltage (V
IN
) any pin
RF/IF mixer input power
Operating Temperature Range
Thermal Resistance (R
TH
)
Storage Temperature Range
Rating
-0.5 to +3.6
-0.3 to V
DD
+ 0.3
+15
-40 to +85
32
-65 to +150
Unit
V
V
dBm
°C
°C/W
°C
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.
Parameter
ESD Requirements
Human Body Model
Charge Device Model
Min.
2000
1500
500
2.7
-40
-0.3
V
DD
/ 1.5
-10
-10
0
0.8*V
DD
10
Specification
Typ.
Max.
Unit
V
V
V
DC Pins
All Pins
All Pins
Condition
Operating Conditions
Supply voltage (V
DD
)
Temperature (T
OP
)
Input low voltage
Input high voltage
Input low current
Input high current
Output low voltage
Output high voltage
Load resistance
Load capacitance
3.0
3.3
+85
+0.5
V
DD
+10
+10
0.2*V
DD
V
DD
20
20
20
25
100
125
Standby
Power Down Current
2
300
-2
10
13
IIP3
Input port frequency range
Mixer input return loss
Output port frequency range
30
30
10
2700
+10
+23
2700
V
°C
V
V
A
A
V
V
kΩ
pF
mA
mA
mA
mA
mA
A
dB
dB
dB
dBm
dBm
MHz
dB
MHz
100Ω differential
Low current, MIX_IDD=1, one mixer enabled.
High linearity, MIX_IDD=6, one mixer enabled.
Reference oscillator and bandgap only.
ENBL=0 and REF_STBY=0
Not including balun losses
Low current setting
High linearity setting
Low current setting
High linearity setting
at V
OL
= 0.6V
at V
OL
= 2.4V
Input = 0V
Input = V
DD
Logic Inputs/Outputs (
V
DD
= Supply to DIG_VDD pin)
GPO Drive Capability
Sink Current
Source Current
Output Impedance
Static
Supply Current (I
DD
) with 1GHz LO
Mixer 1/2 (Mixer output driving 4:1 balun)
Gain
Noise Figure
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DS140110
RFFC2071/2072
Parameter
Reference Oscillator
External reference frequency
Reference divider ratio
External reference input level
Synthesizer output frequency
Phase detector frequency
Phase noise (LO = 1GHz)
-108
-108
-135
0.19
Phase noise (LO = 2GHz)
-102
-102
-130
0.32
Normalized phase noise floor
-214
10
1
500
85
800
104
7
1500
2700
52
mVp-p
MHz
MHz
dBc/Hz
dBc/Hz
dBc/Hz
°
dBc/Hz
dBc/Hz
dBc/Hz
°
dBc/Hz
10kHz offset
100kHz offset
1MHz offset
RMS integrated from 1kHz to 40MHz
10kHz offset
100kHz offset
1MHz offset
RMS integrated from 1kHz to 40MHz
Measured at 20kHz to 30kHz offset
AC-coupled
MHz
Min.
Specification
Typ.
Max.
Unit
Condition
Synthesizer (Loop bandwidth of 200KHz, 52MHz reference)
Voltage Controlled Oscillator
Open loop phase noise at 1MHz
offset
2.5GHz LO frequency
2.0GHz LO frequency
1.5GHz LO frequency
Open loop phase noise at 10MHz
offset
2.5GHz LO frequency
2.0GHz LO frequency
1.5GHz LO frequency
-149
-150
-151
85
0
5400
dBc/Hz
dBc/Hz
dBc/Hz
MHz
dBm
VCO3
VCO2
VCO1
Note Minimum LO Divide by 2 at Mixer
Driven from 50Source Via a 1:1 Balun
-134
-135
-136
dBc/Hz
dBc/Hz
dBc/Hz
VCO3
VCO2
VCO1
External LO Input
LO Input Frequency Range
External LO Input Level
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RFFC2071/2072
Pin Names and Descriptions
Pin
Name
Description
1
ENBL/GPO5
Device Enable pin. See note 1 and 2.
External local oscillator input (see note 4).
2
EXT_LO
3
EXT_LO_DEC
Decoupling pin for external local oscillator (see note 4).
External bandgap bias resistor. See note 3.
4
REXT
5
ANA_VDD1
Analog supply. Use good RF decoupling.
Phase detector output. Low-frequency noise-sensitive node.
6
LFILT1
Loop filter op-amp output. Low-frequency noise-sensitive node.
7
LFILT2
VCO control input. Low-frequency noise-sensitive node.
8
LFILT3
9
MODE/GPO6
Mode select pin. See note 1 and 2.
Reference input. Use AC coupling capacitor.
10
REF_IN
11
NC
Connect to ground.
12
TM
Differential input 1 (see note 4). On RFFC2072 this pin is NC.
13
MIX1_IPN
Differential input 1 (see note 4). On RFFC2072 this pin is NC.
14
MIX1_IPP
15
GPO1/ADD1
General purpose output / MultiSlice address bit.
16
GPO2/ADD2
General purpose output / MultiSlice address bit.
17
MIX1_OPN
Differential output 1 (see note 5). On RFFC2072 this pin is NC.
18
MIX1_OPP
Differential output 1 (see note 5). On RFFC2072 this pin is NC.
Digital supply. Should be decoupled as close to the pin as possible.
19
DIG_VDD
20
NC
21
NC
22
ANA_VDD2
Analog supply. Use good RF decoupling.
Differential input 2 (see note 4).
23
MIX2_IPP
Differential input 2 (see note 4).
24
MIX2_IPN
General purpose output / frequency control input.
25
GPO3/FM
26
GPO4/LD/DO
General purpose output / Lock detect output / serial data out.
27
MIX2_OPN
Differential output 2 (see note 5).
28
MIX2_OPP
Differential output 2 (see note 5).
Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.
29
RESETX
Serial interface select (active low). See note 1.
30
ENX
Serial interface clock. See note 1.
31
SCLK
Serial interface data. See note 1.
32
SDATA
Ground reference, should be connected to PCB ground through a low impedance path.
Exposed paddle
Note 1: An RC low pass filter could be used on this line to reduce digital noise.
Note 2: If the device is under software control this input can be configured as a general purpose output (GPO).
Note 3: Connect a 51kΩ resistor from this pin to ground, this pin is sensitive to low frequency noise injection.
Note 4: DC voltage should not be applied to this pin. Use either an AC-coupling capacitor as part of lumped element matching
network or a transformer (see evaluation board schematic).
Note 5: This pin must be connected to ANA_VDD2 using an RF choke or a transformer (see application schematic).
4 of 23
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DS140110
RFFC2071/2072
Theory of Operation
The RFFC2071 and RFFC2072 are wideband RF frequency converter chips which include a fractional-N synthesizer and a low
noise VCO core. The RFFC2071 has an LO signal multiplexer, two LO buffer circuits, and two RF mixers. The RFFC2072 has a
single LO buffer circuit and one RF mixer. Both devices have an integrated voltage reference and low drop out regulators sup-
plying critical circuit blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are
achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple 3-wire
serial interface.
VCO
The VCO core in the RFFC2071 and RFFC2072 consists of three VCOs which, in conjunction with the integrated LO dividers of
/2 to /32, cover the LO range of 85MHz to 2700MHz. Each VCO has 128 overlapping bands which are used to achieve low VCO
gain and optimal phase noise performance across the whole tuning range. The chip automatically selects the correct VCO (VCO
auto-select) and VCO band (VCO coarse tuning) to generate the desired LO frequency based on the values programmed into
the PLL1 and PLL2 registers banks.
The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is
programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the
band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is
oscillating approximately at the correct frequency. The output of this band selection, CT_CAL, is made available in the read-
back register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this will also be indi-
cated by the CT_FAILED flag also available in the read-back register. A CT_CAL value between 1 and 126 indicates a success-
ful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.
The band select process will center the VCO tuning voltage at about 1.0V, compensating for manufacturing tolerances and pro-
cess variation as well as environmental factors including temperature. In applications where the device is left enabled at the
same LO frequency for some time, it is recommended that automatic band selection be performed for every 30°C change in
temperature. This assumes an active loop filter.
The RFFC2071 and RFFC2072 feature a differential LO input to allow the mixer to be driven from an external LO source. The
fractional-N PLL can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in
some applications. This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.
In the RFFC2071 the LO signal is routed to mixer 1, mixer 2, or both mixers depending on the state of the MODE pin (or MODE
bit if under software control) and the value of the FULLD bit. Setting FULLD high puts the device into Full Duplex mode and both
mixers are enabled.
Fractional-N PLL
The RFFC2071 and RFFC2072 contain a charge pump-based fractional-N phase locked loop (PLL) for controlling the three
VCOs. The PLL includes automatic calibration systems to counteract the effects of process and environmental variations,
ensuring repeatable loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a
loop filter calibration mechanism which can be enabled if required. This operates by adjusting the charge pump current to
maintain loop bandwidth. This can be useful for applications where the LO is tuned over a wide frequency range.
The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is
typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RFFC2071 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automati-
cally as the mixer is selected using MODE. For the RFFC2072 mixer 2 and register bank PLL2 are normally used.
The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters
the N divider, which is a fractional divider containing a dual-modulus prescaler and a digitally spur-compensated fractional
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
5 of 23
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