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NSS40500UW3T2G_12

产品描述40 V, 5.0 A, Low VCE(sat) PNP Transistor
文件大小103KB,共5页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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NSS40500UW3T2G_12概述

40 V, 5.0 A, Low VCE(sat) PNP Transistor

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NSS40501UW3,
NSV40501UW3
40 V, 5.0 A, Low V
CE(sat)
NPN Transistor
ON Semiconductor’s e
2
PowerEdge family of low V
CE(sat)
transistors are miniature surface mount devices featuring ultra low
saturation voltage (V
CE(sat)
) and high current gain capability. These
are designed for use in low voltage, high speed switching applications
where affordable efficient energy control is important.
Typical applications are DC−DC converters and power management
in portable and battery powered products such as cellular and cordless
phones, PDAs, computers, printers, digital cameras and MP3 players.
Other applications are low voltage motor controls in mass storage
products such as disc drives and tape drives. In the automotive
industry they can be used in air bag deployment and in the instrument
cluster. The high current gain allows e
2
PowerEdge devices to be
driven directly from PMU’s control outputs, and the Linear Gain
(Beta) makes them ideal components in analog amplifiers.
Features
http://onsemi.com
40 VOLTS, 5.0 AMPS
NPN LOW V
CE(sat)
TRANSISTOR
EQUIVALENT R
DS(on)
38 mW
COLLECTOR
3
1
BASE
2
EMITTER
3
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(T
A
= 25°C)
Rating
Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage
Collector Current
Continuous
Collector Current
Peak
Electrostatic Discharge
Symbol
V
CEO
V
CBO
V
EBO
I
C
I
CM
ESD
Max
40
40
6.0
5.0
7.0
Unit
Vdc
Vdc
Vdc
Adc
A
2
1
WDFN3
CASE 506AU
MARKING DIAGRAM
VB M
G
G
1
VB = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
HBM Class 3B
MM Class C
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation, T
A
= 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Total Device Dissipation, T
A
= 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Thermal Resistance,
Junction−to−Lead #3
Junction and Storage
Temperature Range
Symbol
P
D
(Note 1)
R
qJA
(Note 1)
P
D
(Note 2)
R
qJA
(Note 2)
R
qJL
(Note 2)
T
J
, T
stg
Max
875
7.0
143
1.5
11.8
85
23
−55
to
+150
Unit
mW
mW/°C
°C/W
W
mW/°C
°C/W
°C/W
°C
ORDERING INFORMATION
Device
NSS40501UW3T2G
NSV40501UW3T2G
Package
WDFN3
(Pb−Free)
WDFN3
(Pb−Free)
Shipping
3000/
Tape & Reel
3000/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ 100 mm
2
, 1 oz copper traces.
2. FR−4 @ 500 mm
2
, 1 oz copper traces.
©
Semiconductor Components Industries, LLC, 2013
August, 2013
Rev. 5
1
Publication Order Number:
NSS40501UW3/D

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描述 40 V, 5.0 A, Low VCE(sat) PNP Transistor 40 V, 5.0 A, Low VCE(sat) NPN Transistor 40 V, 5.0 A, Low VCE(sat) NPN Transistor 40 V, 5.0 A, Low VCE(sat) NPN Transistor

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